FPGA Revolution
FPGA Revolution
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FPGA 34 - Flying Cubes 3D rendering in real-time
In this episode, we're going to be implementing 3D rendering in real time through designing a complete application leveraging both software and hardware capabilities on an SoC FPGA to render a 3D scene filled with an army of cubes of different colors rotating around in space at variable rotation speed.
Github for the project
github.com/fpgarevolution/FlyingCubes3D
มุมมอง: 532

วีดีโอ

FPGA 33 - Game of Pong over HDMI FPGA design13:30FPGA 33 - Game of Pong over HDMI FPGA design
FPGA 33 - Game of Pong over HDMI FPGA design
มุมมอง 1.2K9 หลายเดือนก่อน
In this episode we're going to build a complete game of Pong HDMI FPGA design. We'll code up four RTL modules to handle the game dynamics on top of the TMDS HDMI driver that we developed in the previous episode. One RTL module to handle the bouncing movement of the object. One RTL module to handle the left and right control of the paddle using two push buttons on the pynq-z1 board. The third RT...
FPGA 32 - Transition-minimized differential signaling (TMDS) 1280x720p @60fps RGB video over HDMI10:51FPGA 32 - Transition-minimized differential signaling (TMDS) 1280x720p @60fps RGB video over HDMI
FPGA 32 - Transition-minimized differential signaling (TMDS) 1280x720p @60fps RGB video over HDMI
มุมมอง 1.2K10 หลายเดือนก่อน
We're building a complete FPGA RTL design to generate transition-minimized differential signaling (TMDS) RGB video over HDMI with a resolution of 1280x720p at 60 frames per second. In addition to using two IP blocks for clock synthesis and video timing generation, we'll code up three RTL modules. One to handle TMDS 8b10b data encoding. One to handle the serialization of encoded 10-bit TMDS data...
FPGA 31 - Zynq SoC FPGA Data acquisition to SD card (Acquisition / DMA and record to SD card)8:45FPGA 31 - Zynq SoC FPGA Data acquisition to SD card (Acquisition / DMA and record to SD card)
FPGA 31 - Zynq SoC FPGA Data acquisition to SD card (Acquisition / DMA and record to SD card)
มุมมอง 2.9K10 หลายเดือนก่อน
We're building a complete Zynq SoC FPGA application demonstrating a full data acquisition design where a block of data or potentially any digitized signal can be processed and streamed through DMA to system memory before getting recorded onto an SD card as a binary file. The DMA engine and the GPIO controller gets configured and controlled by software through the AXI4-lite interface. Software u...
FPGA 30 - Zynq SoC FPGA Direct Memory Access (DMA) between PS DDR memory and PL AXI4-Stream FIFO6:42FPGA 30 - Zynq SoC FPGA Direct Memory Access (DMA) between PS DDR memory and PL AXI4-Stream FIFO
FPGA 30 - Zynq SoC FPGA Direct Memory Access (DMA) between PS DDR memory and PL AXI4-Stream FIFO
มุมมอง 5K10 หลายเดือนก่อน
In this episode, we're building a complete Zynq SoC FPGA application demonstrating direct memory access (DMA) in both directions between the processing system's DDR memory and another block of memory with an AXI4-stream interface residing in the programmable logic fabric. The application is validated on the pynq-z1 board. The DMA engine is configured by the C application through the AXI4-Lite i...
FPGA 29 - Zynq SoC FPGA XADC application measures on-chip power supply voltages and die temperature6:10FPGA 29 - Zynq SoC FPGA XADC application measures on-chip power supply voltages and die temperature
FPGA 29 - Zynq SoC FPGA XADC application measures on-chip power supply voltages and die temperature
มุมมอง 1.2K11 หลายเดือนก่อน
In this episode we're going to build a complete Zynq SoC FPGA application utilizing the integrated XADC to measure on-chip power supply voltages and die temperature. These are some of key important parameters whose stability need to be constantly monitored and well-controlled to ensure continuous reliable operation throughout the lifetime of a system. The application is validated on the MiniZed...
FPGA 28 - The power of mixed-mode clock manager6:04FPGA 28 - The power of mixed-mode clock manager
FPGA 28 - The power of mixed-mode clock manager
มุมมอง 74511 หลายเดือนก่อน
In this episode, we're going to look at mixed-mode clock manager primitive or MMCM, one of FPGAs' many powerful capabilities. A mixed-mode clock manager is similar to a phase locked loop or PLL in that both of them can be used to generate multiple clocks with arbitrary defined phase and frequency relationships to a given input clock. But a mixed-mode clock manager has a couple other advanced fe...
FPGA 27 - Zynq SoC FPGA PL interrupts PS to trigger software execution7:25FPGA 27 - Zynq SoC FPGA PL interrupts PS to trigger software execution
FPGA 27 - Zynq SoC FPGA PL interrupts PS to trigger software execution
มุมมอง 2.7K11 หลายเดือนก่อน
In this episode we're building a complete Zynq SoC FPGA application demonstrating an interrupt-based architecture where the programmable logic (PL) has the capability of interrupting the processing system (PS) to trigger the execution of software programs through the interrupt handler. To test this design we would set up a free-running timer to periodically drive a pulse onto the interrupt line...
FPGA 26 - Shared PS-PL AXI BRAM Application on Zynq SoC FPGA (VHDL)7:52FPGA 26 - Shared PS-PL AXI BRAM Application on Zynq SoC FPGA (VHDL)
FPGA 26 - Shared PS-PL AXI BRAM Application on Zynq SoC FPGA (VHDL)
มุมมอง 1.7K11 หลายเดือนก่อน
In this episode, we're building the VHDL version of a complete Zynq SoC FPGA application demonstrating a shared AXI BRAM architecture where both the programmable logic (PL) and the processing system (PS) share a 2K by 32-bit BRAM memory and able to exchange data through this shared BRAM buffer. To test this design, we would initiate writing 32-bit counter data into this shared BRAM from the PL ...
FPGA 25 - Shared PS-PL AXI BRAM Application on Zynq SoC FPGA (Verilog)7:51FPGA 25 - Shared PS-PL AXI BRAM Application on Zynq SoC FPGA (Verilog)
FPGA 25 - Shared PS-PL AXI BRAM Application on Zynq SoC FPGA (Verilog)
มุมมอง 3.1K11 หลายเดือนก่อน
In this episode, we're building a complete Zynq SoC FPGA application demonstrating a shared AXI BRAM architecture where both the programmable logic (PL) and the processing system (PS) share a 2K by 32-bit BRAM memory and able to exchange data through this shared BRAM buffer. To test this design, we would initiate writing 32-bit counter data into this shared BRAM from the PL side upon system res...
FPGA 24 - DSP FIR Lowpass Filter with VHDL7:45FPGA 24 - DSP FIR Lowpass Filter with VHDL
FPGA 24 - DSP FIR Lowpass Filter with VHDL
มุมมอง 2.6K11 หลายเดือนก่อน
In this episode, we're building a 9-tap finite impulse response (FIR) lowpass filter in VHDL that has a cutoff frequency at ~10MHz with a 100MHz sampling clock. In order to test this FIR lowpass filter, we're also building a testbench that synthesize two sine waves, one at 2MHz and the other at 30MHz. These two sine waves are added together and the resulting noisy signal is resampled at 100MHz ...
FPGA 23 - DSP FIR Lowpass Filter with Verilog7:29FPGA 23 - DSP FIR Lowpass Filter with Verilog
FPGA 23 - DSP FIR Lowpass Filter with Verilog
มุมมอง 7K11 หลายเดือนก่อน
In this episode, we're building a 9-tap finite impulse response (FIR) lowpass filter in Verilog that has a cutoff frequency at ~10MHz with a 100MHz sampling clock. In order to test this FIR lowpass filter, we're also building a testbench that synthesize two sine waves, one at 2MHz and the other at 30MHz. These two sine waves are added together and the resulting noisy signal is resampled at 100M...
FPGA 22 - How to do VHDL parameterization4:29FPGA 22 - How to do VHDL parameterization
FPGA 22 - How to do VHDL parameterization
มุมมอง 12011 หลายเดือนก่อน
A hands-on tutorial on how to do parameterization with VHDL. #fpga #vhdl #simulation #logic
FPGA 21 - How to do Verilog parameterization4:06FPGA 21 - How to do Verilog parameterization
FPGA 21 - How to do Verilog parameterization
มุมมอง 12311 หลายเดือนก่อน
A hands-on tutorial on how to do parameterization with Verilog. #fpga #verilog #simulation #logic
FPGA 20 - Build complete Zynq SoC FPGA application for PYNQ-Z1 with software control of AXI GPIO LED6:33FPGA 20 - Build complete Zynq SoC FPGA application for PYNQ-Z1 with software control of AXI GPIO LED
FPGA 20 - Build complete Zynq SoC FPGA application for PYNQ-Z1 with software control of AXI GPIO LED
มุมมอง 54311 หลายเดือนก่อน
FPGA 20 - Build complete Zynq SoC FPGA application for PYNQ-Z1 with software control of AXI GPIO LED
FPGA 19 - AMD Xilinx VHDL CORDIC Sine/Cosine generator4:42FPGA 19 - AMD Xilinx VHDL CORDIC Sine/Cosine generator
FPGA 19 - AMD Xilinx VHDL CORDIC Sine/Cosine generator
มุมมอง 2.2Kปีที่แล้ว
FPGA 19 - AMD Xilinx VHDL CORDIC Sine/Cosine generator
FPGA 18 - AMD Xilinx Verilog CORDIC Sine/Cosine generator4:18FPGA 18 - AMD Xilinx Verilog CORDIC Sine/Cosine generator
FPGA 18 - AMD Xilinx Verilog CORDIC Sine/Cosine generator
มุมมอง 3.9Kปีที่แล้ว
FPGA 18 - AMD Xilinx Verilog CORDIC Sine/Cosine generator
FPGA 17 - Intel Altera VHDL CORDIC Sine/Cosine generator7:06FPGA 17 - Intel Altera VHDL CORDIC Sine/Cosine generator
FPGA 17 - Intel Altera VHDL CORDIC Sine/Cosine generator
มุมมอง 857ปีที่แล้ว
FPGA 17 - Intel Altera VHDL CORDIC Sine/Cosine generator
FPGA 16 - Intel Altera Verilog CORDIC Sine/Cosine generator5:58FPGA 16 - Intel Altera Verilog CORDIC Sine/Cosine generator
FPGA 16 - Intel Altera Verilog CORDIC Sine/Cosine generator
มุมมอง 656ปีที่แล้ว
FPGA 16 - Intel Altera Verilog CORDIC Sine/Cosine generator
FPGA 15 - Xilinx Zynq SoC FPGA Build your first "hello world" program6:57FPGA 15 - Xilinx Zynq SoC FPGA Build your first "hello world" program
FPGA 15 - Xilinx Zynq SoC FPGA Build your first "hello world" program
มุมมอง 765ปีที่แล้ว
FPGA 15 - Xilinx Zynq SoC FPGA Build your first "hello world" program
FPGA 14 - VHDL Quartus/Questa finite-state machine design8:35FPGA 14 - VHDL Quartus/Questa finite-state machine design
FPGA 14 - VHDL Quartus/Questa finite-state machine design
มุมมอง 384ปีที่แล้ว
FPGA 14 - VHDL Quartus/Questa finite-state machine design
FPGA 13 - Verilog Quartus/Questa finite-state machine design7:54FPGA 13 - Verilog Quartus/Questa finite-state machine design
FPGA 13 - Verilog Quartus/Questa finite-state machine design
มุมมอง 356ปีที่แล้ว
FPGA 13 - Verilog Quartus/Questa finite-state machine design
FPGA 12 - VHDL Vivado finite-state machine design8:17FPGA 12 - VHDL Vivado finite-state machine design
FPGA 12 - VHDL Vivado finite-state machine design
มุมมอง 592ปีที่แล้ว
FPGA 12 - VHDL Vivado finite-state machine design
FPGA 11 - Verilog Vivado finite-state machine design7:47FPGA 11 - Verilog Vivado finite-state machine design
FPGA 11 - Verilog Vivado finite-state machine design
มุมมอง 770ปีที่แล้ว
FPGA 11 - Verilog Vivado finite-state machine design
FPGA 10 - VHDL Quartus/Questa two's complement fixed-point arithmetic9:32FPGA 10 - VHDL Quartus/Questa two's complement fixed-point arithmetic
FPGA 10 - VHDL Quartus/Questa two's complement fixed-point arithmetic
มุมมอง 286ปีที่แล้ว
FPGA 10 - VHDL Quartus/Questa two's complement fixed-point arithmetic
FPGA 9 - Verilog Quartus/Questa two's complement fixed-point arithmetic7:30FPGA 9 - Verilog Quartus/Questa two's complement fixed-point arithmetic
FPGA 9 - Verilog Quartus/Questa two's complement fixed-point arithmetic
มุมมอง 367ปีที่แล้ว
FPGA 9 - Verilog Quartus/Questa two's complement fixed-point arithmetic
FPGA 8 - VHDL Vivado two's complement fixed-point arithmetic8:15FPGA 8 - VHDL Vivado two's complement fixed-point arithmetic
FPGA 8 - VHDL Vivado two's complement fixed-point arithmetic
มุมมอง 638ปีที่แล้ว
FPGA 8 - VHDL Vivado two's complement fixed-point arithmetic
FPGA 7 - Verilog Vivado two's complement fixed-point arithmetic8:24FPGA 7 - Verilog Vivado two's complement fixed-point arithmetic
FPGA 7 - Verilog Vivado two's complement fixed-point arithmetic
มุมมอง 1Kปีที่แล้ว
FPGA 7 - Verilog Vivado two's complement fixed-point arithmetic
FPGA 6 - First VHDL Quartus/Questa project for beginners7:43FPGA 6 - First VHDL Quartus/Questa project for beginners
FPGA 6 - First VHDL Quartus/Questa project for beginners
มุมมอง 1.4Kปีที่แล้ว
FPGA 6 - First VHDL Quartus/Questa project for beginners
FPGA 5 - First Verilog Quartus/Questa project for beginners6:16FPGA 5 - First Verilog Quartus/Questa project for beginners
FPGA 5 - First Verilog Quartus/Questa project for beginners
มุมมอง 1.4Kปีที่แล้ว
FPGA 5 - First Verilog Quartus/Questa project for beginners

ความคิดเห็น

  • @NithinVarghese-zk4vt
    @NithinVarghese-zk4vt 18 ชั่วโมงที่ผ่านมา

    can you do a video on read and write in NVME SSD?

  • @snevinleoneel8105
    @snevinleoneel8105 2 วันที่ผ่านมา

    Hi, Could you please show the implications of the same in Quartus? I tried but stuck at errors related to IP.

  • @LOCHA-fc3km
    @LOCHA-fc3km 8 วันที่ผ่านมา

    You are awesome, keep going

  • @yanjiahao8772
    @yanjiahao8772 18 วันที่ผ่านมา

    Thank you so much, it's the best approach I found so far, really helps me figure out my fir filter design multiplier block, appreciate a lot!

  • @mannguyen5781
    @mannguyen5781 24 วันที่ผ่านมา

    hi, i have a question, and I need your assistance. When does DMA stop reading? Many thanks.

  • @17charles5
    @17charles5 28 วันที่ผ่านมา

    搖旗倒讃 高歌離席

  • @pauleyermann651
    @pauleyermann651 หลายเดือนก่อน

    If you want the video to be useful please remove that stupid music and click around more slowly

  • @adelynul
    @adelynul หลายเดือนก่อน

    Music name?

  • @muhammedalikaya268
    @muhammedalikaya268 หลายเดือนก่อน

    Thanks sir, I want to show a picture on the HDMI monitor. For this, I load the image data from block ram as a coe file. Would it be enough if I use the tmds_encode, tmds_oserdes and hdmi_transmit modules as you did to do the HDMI part?

  • @GauravKatiyar-yi8ro
    @GauravKatiyar-yi8ro หลายเดือนก่อน

    fir_tb.v module fir_tb(); localparam CORDIC_CLK_PERIOD = 1250; // Clock period for the CORDIC at 800 Hz localparam FIR_CLK_PERIOD = 1250; // Clock period for the FIR filter at 800 Hz localparam signed [15:0] PI_POS = 16'h6488; // Positive PI constant localparam signed [15:0] PI_NEG = 16'h9878; // Negative PI constant localparam PHASE_INC_150HZ = 122; // Phase increment for 150 Hz signal at 800 Hz localparam PHASE_INC_400HZ = 326; // Phase increment for 400 Hz signal at 800 Hz reg cordic_clk = 1'b0; reg fir_clk = 1'b0; reg phase_tvalid = 1'b0; reg signed [15:0] phase_150Hz = 0; reg signed [15:0] phase_400Hz = 0; wire sincos_150Hz_tvalid; wire signed [15:0] sin_150Hz, cos_150Hz; wire sincos_400Hz_tvalid; wire signed [15:0] sin_400Hz, cos_400Hz; reg signed [15:0] noisy_signal = 0; wire signed [15:0] filtered_signal; // Instantiate CORDIC for 150 Hz sine wave generation // Ensure cordic_0 is defined or imported in your project cordic_0 cordic_inst_150Hz( .aclk(cordic_clk), .s_axis_phase_tvalid(phase_tvalid), .s_axis_phase_tdata(phase_150Hz), .m_axis_dout_tvalid(sincos_150Hz_tvalid), .m_axis_dout_tdata({sin_150Hz, cos_150Hz}) ); // Instantiate CORDIC for 400 Hz sine wave generation cordic_0 cordic_inst_400Hz( .aclk(cordic_clk), .s_axis_phase_tvalid(phase_tvalid), .s_axis_phase_tdata(phase_400Hz), .m_axis_dout_tvalid(sincos_400Hz_tvalid), .m_axis_dout_tdata({sin_400Hz, cos_400Hz}) ); // Phase sweep for 150 Hz and 400 Hz sine wave generation always @(posedge cordic_clk) begin phase_tvalid <= 1'b1; // Update phase for 150 Hz sine wave if (phase_150Hz + PHASE_INC_150HZ < PI_POS) begin phase_150Hz <= phase_150Hz + PHASE_INC_150HZ; end else begin phase_150Hz <= PI_NEG + (phase_150Hz + PHASE_INC_150HZ - PI_POS); end // Update phase for 400 Hz sine wave if (phase_400Hz + PHASE_INC_400HZ < PI_POS) begin phase_400Hz <= phase_400Hz + PHASE_INC_400HZ; end else begin phase_400Hz <= PI_NEG + (phase_400Hz + PHASE_INC_400HZ - PI_POS); end end // Create 800 Hz Cordic clock always begin #(CORDIC_CLK_PERIOD / 2) cordic_clk = ~cordic_clk; end // Create 800 Hz FIR clock always begin #(FIR_CLK_PERIOD / 2) fir_clk = ~fir_clk; end // Generate the noisy signal by mixing 150 Hz and 400 Hz sine waves always @(posedge fir_clk) begin noisy_signal <= (sin_150Hz + sin_400Hz) >>> 1; // Average the sum of 150 Hz and 400 Hz sine waves end // Instantiate the 5-tap FIR filter module // Ensure fir_5tap is properly defined and imported in your project fir fir_5tap( .clk(fir_clk), .noisy_signal(noisy_signal), .filtered_signal(filtered_signal) ); endmodule

  • @user-tp8ht3ih2t
    @user-tp8ht3ih2t 2 หลายเดือนก่อน

    Code is not running

  • @user-py6zc5gx3l
    @user-py6zc5gx3l 2 หลายเดือนก่อน

    could the design be shared? maybe tcl

  • @edward4061
    @edward4061 2 หลายเดือนก่อน

    Hi thanks for the tutorial. What changes i have to do if i want to send data from PL AXI SPI to PS DDR3 using DMA

  • @theoryandapplication7197
    @theoryandapplication7197 2 หลายเดือนก่อน

    thank you sir

  • @ArjunRam-pr5yb
    @ArjunRam-pr5yb 2 หลายเดือนก่อน

    please can you tell how its actually cofficient convert into hexadecimal value? it will be very help for me

  • @Serinebey13
    @Serinebey13 2 หลายเดือนก่อน

    You're a legend! I've watched numerous tutorials, but when it comes to the test bench, you're the only one who writes the code from scratch. Major respect!

  • @donaldkelly3016
    @donaldkelly3016 2 หลายเดือนก่อน

    When I build and debug as hardware, exit.c opens breakpoints at line16 and has unresolved inclusion of unistd.h commenting out sections of exit.c or entirety of exit.c does not resolve. exit.c is pausing the program right after successful print of "Zynq SoC acquisition to SD card", so right before initialization of drivers or at the initialization of the first driver. It appears that the initialization of the GPIO driver is maybe failing. I was getting following warning for XAxiDma_SimpleTransfer: passing argument 2 of 'XAxiDma_SimpleTransfer' makes integer from pointer without a cast [-Wint-conversion] I also had to change byte written to a UINT. Looks like XAxiDMA_SimpleTransfer wants a pointer, not an array for the 2nd argument. I the warning goes away when you dereference buf_acq_to_dma by passing "*buf_acq_to_dma" xilinx.github.io/embeddedsw.github.io/axidma/doc/html/api/group___a_x_i_d_m_a.html#ga32ca6099d7926297a4c17cdb4a19511b

  • @tl.nguyen.27
    @tl.nguyen.27 3 หลายเดือนก่อน

    Can I ask how to convert -91.75 to 16'h A440?

    • @vinisharamkumar4181
      @vinisharamkumar4181 2 หลายเดือนก่อน

      The number representation followed is signed 2's complement. So the msb bit represents the sign For negative number sign bit is 1 and the remaining bits will be a 2s complete. A and B is 16 bit, and fractional value is 8 bit long and integer value is 8 bit long 1. Convert A440 to binary 1010010001000000 2. The msb denotes it's a negative number .so take 2s completement of the remaining number. 3. Be careful while considering the decimal point

  • @shravanilakhote7338
    @shravanilakhote7338 3 หลายเดือนก่อน

    Sir , is it okay to store the data in the bram using .coe file ? and how do you read the contents of the memory without using hardware ? is there any specific tcl command for that or i can read it through simulation ?

  • @user-jz4pl1wb4p
    @user-jz4pl1wb4p 3 หลายเดือนก่อน

    XPAR_AXI_BRAM_CTRL_0_S_AXI_BASEADDR variable is auto generation????

  • @user-ti6zs3xd1z
    @user-ti6zs3xd1z 3 หลายเดือนก่อน

    I would change the respective part of the code to this: begin phase_tvalid <= 1'b1; if ($signed(phase) + $signed(PHASE_INC) < $signed(PI_POS)) begin phase <= phase + PHASE_INC; end else begin phase <= PI_NEG; end end

  • @dillanrainerpereira806
    @dillanrainerpereira806 3 หลายเดือนก่อน

    Thank You

    • @GauravKatiyar-yi8ro
      @GauravKatiyar-yi8ro หลายเดือนก่อน

      module fir_tb(); localparam CORDIC_CLK_PERIOD = 1250; // Clock period for the CORDIC at 800 Hz localparam FIR_CLK_PERIOD = 1250; // Clock period for the FIR filter at 800 Hz localparam signed [15:0] PI_POS = 16'h6488; // Positive PI constant localparam signed [15:0] PI_NEG = 16'h9878; // Negative PI constant localparam PHASE_INC_150HZ = 122; // Phase increment for 150 Hz signal at 800 Hz localparam PHASE_INC_400HZ = 326; // Phase increment for 400 Hz signal at 800 Hz reg cordic_clk = 1'b0; reg fir_clk = 1'b0; reg phase_tvalid = 1'b0; reg signed [15:0] phase_150Hz = 0; reg signed [15:0] phase_400Hz = 0; wire sincos_150Hz_tvalid; wire signed [15:0] sin_150Hz, cos_150Hz; wire sincos_400Hz_tvalid; wire signed [15:0] sin_400Hz, cos_400Hz; reg signed [15:0] noisy_signal = 0; wire signed [15:0] filtered_signal; // Instantiate CORDIC for 150 Hz sine wave generation // Ensure cordic_0 is defined or imported in your project cordic_0 cordic_inst_150Hz( .aclk(cordic_clk), .s_axis_phase_tvalid(phase_tvalid), .s_axis_phase_tdata(phase_150Hz), .m_axis_dout_tvalid(sincos_150Hz_tvalid), .m_axis_dout_tdata({sin_150Hz, cos_150Hz}) ); // Instantiate CORDIC for 400 Hz sine wave generation cordic_0 cordic_inst_400Hz( .aclk(cordic_clk), .s_axis_phase_tvalid(phase_tvalid), .s_axis_phase_tdata(phase_400Hz), .m_axis_dout_tvalid(sincos_400Hz_tvalid), .m_axis_dout_tdata({sin_400Hz, cos_400Hz}) ); // Phase sweep for 150 Hz and 400 Hz sine wave generation always @(posedge cordic_clk) begin phase_tvalid <= 1'b1; // Update phase for 150 Hz sine wave if (phase_150Hz + PHASE_INC_150HZ < PI_POS) begin phase_150Hz <= phase_150Hz + PHASE_INC_150HZ; end else begin phase_150Hz <= PI_NEG + (phase_150Hz + PHASE_INC_150HZ - PI_POS); end // Update phase for 400 Hz sine wave if (phase_400Hz + PHASE_INC_400HZ < PI_POS) begin phase_400Hz <= phase_400Hz + PHASE_INC_400HZ; end else begin phase_400Hz <= PI_NEG + (phase_400Hz + PHASE_INC_400HZ - PI_POS); end end // Create 800 Hz Cordic clock always begin #(CORDIC_CLK_PERIOD / 2) cordic_clk = ~cordic_clk; end // Create 800 Hz FIR clock always begin #(FIR_CLK_PERIOD / 2) fir_clk = ~fir_clk; end // Generate the noisy signal by mixing 150 Hz and 400 Hz sine waves always @(posedge fir_clk) begin noisy_signal <= (sin_150Hz + sin_400Hz) >>> 1; // Average the sum of 150 Hz and 400 Hz sine waves end // Instantiate the 5-tap FIR filter module // Ensure fir_5tap is properly defined and imported in your project fir fir_5tap( .clk(fir_clk), .noisy_signal(noisy_signal), .filtered_signal(filtered_signal) ); endmodule

  • @sw3916
    @sw3916 3 หลายเดือนก่อน

    Hi thanks for the video, dont you need to connect the fixed_io and DDR pins of the Zynq7 block in the PL via the auto connect?

  • @alneidit3760
    @alneidit3760 3 หลายเดือนก่อน

    Bro pls upload the code bro

  • @bhavanar6501
    @bhavanar6501 4 หลายเดือนก่อน

    can u send the code please

  • @jonggeunlim6151
    @jonggeunlim6151 4 หลายเดือนก่อน

    Nice video

  • @sirashsayanju793
    @sirashsayanju793 4 หลายเดือนก่อน

    This is really awesome

  • @user-rw7np
    @user-rw7np 4 หลายเดือนก่อน

    can't we do this without using PS part i.e, by writing a verilog code and can't we implement on board

    • @FPGARevolution
      @FPGARevolution 4 หลายเดือนก่อน

      Yes you can access the XADC from either the PL or the PS.

  • @user-vj3cx3hj9g
    @user-vj3cx3hj9g 4 หลายเดือนก่อน

    thanks for this tutorial video

  • @chuckwright6395
    @chuckwright6395 4 หลายเดือนก่อน

    You should have filtered out the background noise in the video.

  • @b213videoz
    @b213videoz 4 หลายเดือนก่อน

    This is a VERY nice show off though NOT a tutorial

  • @aranyagupta8588
    @aranyagupta8588 5 หลายเดือนก่อน

    .addra(bram_porta_0_addr[12:2]) kindly let me know why the PART A has [12:2] not [12:0].

    • @FPGARevolution
      @FPGARevolution 4 หลายเดือนก่อน

      32-bit addressing example

    • @aranyagupta354
      @aranyagupta354 4 หลายเดือนก่อน

      ​@@FPGARevolution Can you tell me if I want to store 64-bit data to BRAM memory and print it through UART, In which steps I need to make changes? I have tried by changing index to 64 bit in both BRAM controller and Block memory and using the following code to print data using UART: #include <stdio.h> #include "platform.h" #include "xil_printf.h" int main () { u64 *address = NULL; init_platform(); print("BRAM Test successful. "); address = (u64 *) XPAR_AXI_BRAM_CTRL_0_S_AXI_BASEADDR; for (u32 i=0; i<2048; i++) { printf("Memory location %d: 0x%llx ", i, *(address+i)); } cleanup_platform(); return 0; } For, 32 bit data it is printing 2048 memory locations but when print 64-bit, it is printing 1024 locations only. Kindly help me out

    • @aranyagupta354
      @aranyagupta354 4 หลายเดือนก่อน

      @@FPGARevolution Can you tell me if I want to store 64-bit data to BRAM memory and print it through UART, In which steps I need to make changes? I have tried by changing index to 64 bit in both BRAM controller and Block memory and using the following code to print data using UART: #include <stdio.h> #include "platform.h" #include "xil_printf.h" int main () { u64 *address = NULL; init_platform(); print("BRAM Test successful. "); address = (u64 *) XPAR_AXI_BRAM_CTRL_0_S_AXI_BASEADDR; for (u32 i=0; i<10; i++) { printf("Memory location %d: 0x%llx ", i, *(address+i)); } cleanup_platform(); return 0; } For, 32 bit data it is printing for 2048 memory locations but when print 64-bit, it is printing 1024 locations only.

  • @korayk.454
    @korayk.454 5 หลายเดือนก่อน

    Thanks for the video! I got error building the project it seems the MKFS_PARM is not defined.. Whout would be the solution? Yes I am a noob:)

  • @DH-fu7bx
    @DH-fu7bx 5 หลายเดือนก่อน

    What about an IIR filter?

    • @FPGARevolution
      @FPGARevolution 4 หลายเดือนก่อน

      It'll show up.

    • @DH-fu7bx
      @DH-fu7bx 4 หลายเดือนก่อน

      @@FPGARevolution Cool! Because I'm a massive noob.

  • @mksaksmsbd
    @mksaksmsbd 5 หลายเดือนก่อน

    The rst signal in top.v file always keep resetting after 2 seconds. And the sw signal never reach 2'b10

  • @Ghhrjovi
    @Ghhrjovi 5 หลายเดือนก่อน

    good work!

  • @mksaksmsbd
    @mksaksmsbd 5 หลายเดือนก่อน

    Hello , I am passing hard time to make it workable. Could you please share the source files ? I was trying to implement the 33 Video. But couldnt make it work. For that I was starting to implement this one. But even for this one I am getting constant flickr.

    • @FPGARevolution
      @FPGARevolution 5 หลายเดือนก่อน

      Check out episode 34

  • @mksaksmsbd
    @mksaksmsbd 5 หลายเดือนก่อน

    Hello , I am passing hard time to make it workable. Could you please share the source files ?

    • @FPGARevolution
      @FPGARevolution 5 หลายเดือนก่อน

      Check out episode 34

    • @mksaksmsbd
      @mksaksmsbd 5 หลายเดือนก่อน

      I checked out but couldnt solve the problem. But could u please share the src files from 33 ? @@FPGARevolution

  • @angelg3986
    @angelg3986 5 หลายเดือนก่อน

    Nice video. Do you have another showing how an FPGA on the PCIE bus of a PC can do DMA C2H via PCIE ?

  • @skywalkerluke-7705
    @skywalkerluke-7705 5 หลายเดือนก่อน

    Hi want to generate frequencies kin khz so is there any formula for input clk and phase increment

    • @FPGARevolution
      @FPGARevolution 5 หลายเดือนก่อน

      The phase resolution is fixed in this IP and the total number of steps is 2*PI or 51,472. The equation for synthesizing the exact frequency is Fout = (phase_jump * sampling_frequency) / 51,472 so plug in your required Fout and tune the two parameters in the numerator accordingly.

    • @skywalkerluke-7705
      @skywalkerluke-7705 5 หลายเดือนก่อน

      @@FPGARevolution thanks

  • @yogaesawibowofransiskus6625
    @yogaesawibowofransiskus6625 5 หลายเดือนก่อน

    do you upload the code online?

    • @FPGARevolution
      @FPGARevolution 5 หลายเดือนก่อน

      Check out episode 34

  • @mannguyen5781
    @mannguyen5781 6 หลายเดือนก่อน

    could you show me the way to integrate it into SoC System (qsys or platform designer), please? Thank you so much.

  • @SanjanaS-ot9xe
    @SanjanaS-ot9xe 6 หลายเดือนก่อน

    sir.. can we use this design for zedboard sir? for accessing ddr memory

    • @FPGARevolution
      @FPGARevolution 5 หลายเดือนก่อน

      Yes but make sure to select the right Zynq device and let the tool generate drivers

  • @co9681
    @co9681 6 หลายเดือนก่อน

    Could you implement QPSK demodulation on a 7010 Zync 🙏

  • @skywalkerluke-7705
    @skywalkerluke-7705 6 หลายเดือนก่อน

    Hi, how did you generate coefficients values in hex format and i want to generate 2khz frequency, what changes should i do.

  • @user-pg8tp2pi5o
    @user-pg8tp2pi5o 6 หลายเดือนก่อน

    hi! I was just wondering how you determined the frequencies of sine wave by the phase jump in testbench, if there are any formula or some references, I would be very appreciate! thank you!

    • @FPGARevolution
      @FPGARevolution 6 หลายเดือนก่อน

      The phase resolution is fixed in this IP and the total number of steps is 2*PI or 51,472. The equation for synthesizing the exact frequency is Fout = (phase_jump * sampling_frequency) / 51,472 so plug in your required Fout and tune the two parameters in the numerator accordingly.

  • @oliverlabert
    @oliverlabert 6 หลายเดือนก่อน

    thanks!

  • @user-wm3hw6jy5l
    @user-wm3hw6jy5l 7 หลายเดือนก่อน

    love you

    • @GauravKatiyar-yi8ro
      @GauravKatiyar-yi8ro หลายเดือนก่อน

      module fir( input wire clk, input wire signed [15:0] noisy_signal, output wire signed [15:0] filtered_signal ); // Declare the loop variable here, outside the always block integer i; integer j; // Coefficients for 5-tap FIR filter //reg signed [15:0] coeff [0:4] = {16'h04F6, 16'h0AE4, 16'h160F, 16'h0AE4, 16'h04F6}; reg signed [15:0] coeff [0:4]; initial begin coeff[0] = 16'h04F6; coeff[1] = 16'h0AE4; coeff[2] = 16'h160F; coeff[3] = 16'h0AE4; coeff[4] = 16'h04F6; end // Delayed signals for the FIR filter reg signed [15:0] delayed_signal [0:4]; // Multiplication products reg signed [31:0] prod [0:4]; // Accumulation stages reg signed [32:0] sum_0 [0:2]; reg signed [33:0] sum_1; // Delay line and pipeline the noisy signal always @(posedge clk) begin // Declare the loop variable outside the loop delayed_signal[0] <= noisy_signal; for (i = 1; i <= 4; i = i + 1) begin delayed_signal[i] <= delayed_signal[i - 1]; end end // Multiply delayed signals with coefficients always @(posedge clk) begin // Loop variable j is already declared at the module level for (j = 0; j <= 4; j = j + 1) begin prod[j] <= delayed_signal[j] * coeff[j]; end end // Accumulate multiplication products always @(posedge clk) begin sum_0[0] <= prod[0] + prod[1]; sum_0[1] <= prod[2]; sum_0[2] <= prod[3] + prod[4]; end // Final summation always @(posedge clk) begin sum_1 <= sum_0[0] + sum_0[1] + sum_0[2]; end // Assign filtered signal output by taking the desired bits of the final sum assign filtered_signal = sum_1[33:18]; // Cast the range of sum_1[33:18] to the type of filtered_signal endmodule

  • @dungtranvan741
    @dungtranvan741 7 หลายเดือนก่อน

    Great!!!! Can you design block FFT 16 or 32 point using pipeline algorithm code vhdl ???? Please!!!!!