FPGA 27 - Zynq SoC FPGA PL interrupts PS to trigger software execution

In this episode we're building a complete Zynq SoC FPGA application demonstrating an interrupt-based architecture where the programmable logic (PL) has the capability of interrupting the processing system (PS) to trigger the execution of software programs through the interrupt handler.
To test this design we would set up a free-running timer to periodically drive a pulse onto the interrupt line every 3 seconds. The system is set up to trigger on the rising edge of the interrupt line and the interrupt handler on the PS side is set up to keep track and count the number of times it sees the interrupt.
The complete application is validated on the MiniZed board.
#fpga #zynq #vivado #vitis #embedded #xilinx #adc
Related Zynq SoC FPGA episodes:
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FPGA 26 - Shared PS-PL AXI BRAM Application on Zynq SoC FPGA (VHDL)
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FPGA 25 - Shared PS-PL AXI BRAM Application on Zynq SoC FPGA (Verilog)
• FPGA 25 - Shared PS-PL...
FPGA 20 - Build complete Zynq SoC FPGA application for PYNQ-Z1 with software control of AXI GPIO LEDs
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Recommended prerequisites:
FPGA 1 - Set up AMD Xilinx Vivado/Vitis (free version)
• FPGA 1 - Set up AMD Xi...
FPGA 3 - First Verilog Vivado project for beginners
• FPGA 3 - First Verilog...
FPGA 4 - First VHDL Vivado project for beginners
• FPGA 4 - First VHDL Vi...
FPGA 15 - Xilinx Zynq SoC FPGA Build your first "hello world" program
• FPGA 15 - Xilinx Zynq ...

[@Ghhrjovi]

good work!

[@vinitapte4265]

If you want the video to be useful please remove that stupid music

[@user-py6zc5gx3l]

@vinitapte4265, why don't you try clicking on the mute button on the bottom right :_ ) ?

[@pauleyermann651]

If you want the video to be useful please remove that stupid music and
click around more slowly