FPGA 18 - AMD Xilinx Verilog CORDIC Sine/Cosine generator

A hands-on tutorial on sine/cosine waveform generation using CORDIC algorithm IP through AMD Xilinx Vivado Verilog design flow.
#fpga #vivado #verilog #xilinx #amd #simulation #trigonometry #dsp

[@17charles5]

搖旗倒讃 高歌離席

[@JamesLee-ub4rm]

超爛

[@sirashsayanju793]

This is really awesome

[@user-ti6zs3xd1z]

I would change the respective part of the code to this:
begin
phase_tvalid

[@Hy34327]

Thank you very much for the video. However, this error occures when I run simulate :( Do you happen to know what to do?
[USF-XSim-62] 'compile' step failed with error(s). Please check the Tcl console output or 'C:/xup/Individual project/sincos/sincos.sim/sim_1/behav/xsim/xvlog.log' file for more information.
[Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.

[@FPGARevolution]

Pay attention to what the error messages tell you and follow them closely. It's complaining about failure during the 'compile' step. You can follow the log file and see where the error is. The console outputs in the lower right window of Vivado also display these error logs. Most likely you have a typo error somewhere in your code and the error log would tell you exactly at which line in your code it sees the error.

[@Hy34327]

@@FPGARevolutionthank you very much for feedback! as a beginner of the FPGA, this kind of video helps A LOT. I really love it

[@skywalkerluke-7705]

Hi want to generate frequencies kin khz so is there any formula for input clk and phase increment

[@FPGARevolution]

The phase resolution is fixed in this IP and the total number of steps is 2*PI or 51,472. The equation for synthesizing the exact frequency is Fout = (phase_jump * sampling_frequency) / 51,472 so plug in your required Fout and tune the two parameters in the numerator accordingly.

[@skywalkerluke-7705]

@@FPGARevolution thanks

[@mayankjoshi7689]

COS AND SIN ARE NOT ABLE TO LOAD THE VALUE

[@FPGARevolution]

If you follow closely and the simulation does not report any specific error, you should be able to reproduce the exact results as demonstrated.

[@Abhishek_78]

I had same observation, double checked my code and found I had not supplied clk from top module to cordic instance correctly
on giving "clk" variable on both places, was able to observe the sinusoidal waveforms

[@NarutoUzumaki-hu2rp]

What is +pi in here

[@FPGARevolution]

It's the positive version of pi.

[@NarutoUzumaki-hu2rp]

@@FPGARevolution thanks