FPGA 31 - Zynq SoC FPGA Data acquisition to SD card (Acquisition / DMA and record to SD card)
ฝัง
- เผยแพร่เมื่อ 3 ต.ค. 2024
- We're building a complete Zynq SoC FPGA application demonstrating a full data acquisition design where a block of data or potentially any digitized signal can be processed and streamed through DMA to system memory before getting recorded onto an SD card as a binary file.
The DMA engine and the GPIO controller gets configured and controlled by software through the AXI4-lite interface. Software uses the GPIO controller to access the acquisition enable signal to ensure proper initialization of the front-end data path as well as the timely start of the data acquisition phase.
Some RTL is constructed to represent the digitized signal at the front end of the data acquisition path as a block of 64 32-bit incrementing numbers. This block of data gets transferred first to a FIFO and to the DMA engine through the AXI4-stream interface before getting DMA-written into system memory through the standard AXI4 interface and recorded to the SD card as a binary file.
#fpga #zynq #vivado #vitis #embedded #verilog #xilinx #dataacquisition
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can you do a video on read and write in NVME SSD?
Thanks for the video! I got error building the project it seems the MKFS_PARM is not defined.. Whout would be the solution? Yes I am a noob:)
Awesome video!
Tried to implement this on my PYNQ-Z1 board, but the DMA is constantly busy, even after the initialization.
I'm using 2023.1 workspace, same as you.
I saw that it is a common problem, but have not found a solution.
Do you know the solution for it?
If you follow all the steps as is, things should come out working as demonstrated, unless you add your own changes that have not been verified. Have a careful review to make sure you didn't miss any connections and that software drivers were generated properly without any reported errors then re-check the status of your DMA channel before you actually start to use it. If you can't seem to have proper initialization of your DMA channel early in the application, that's a good hint that you mess up somewhere and the bug is much simpler than if it was something that shows up dynamically. Review your software initialization and if it seems solid then review your hardware block design of the DMA channel.
Yep, somehow forgot tkeep signal, that was the problem.
Thanks :)@@FPGARevolution