FPGA 7 - Verilog Vivado two's complement fixed-point arithmetic

แชร์
ฝัง
  • เผยแพร่เมื่อ 3 ต.ค. 2024

ความคิดเห็น • 4

  • @yanjiahao8772
    @yanjiahao8772 3 หลายเดือนก่อน

    Thank you so much, it's the best approach I found so far, really helps me figure out my fir filter design multiplier block, appreciate a lot!

  • @amirchernin7254
    @amirchernin7254 21 ชั่วโมงที่ผ่านมา

    Is it a good practice to multiply numbers like that in verilog? I am dealing with some floating point calculations in one of my projects, and I need to calculate the multiplication of two 32 bit numbers.
    I used a multiplier block that has some latency, and had to do some coding and testbenching to make sure it works properly.
    I managed to make it work through pipelining the data, but it would be a lot easier to just use "*".
    But I'm not sure how the synthesizer would do it. I remember once getting time issues for something like that.

  • @tl.nguyen.27
    @tl.nguyen.27 6 หลายเดือนก่อน

    Can I ask how to convert -91.75 to 16'h A440?

    • @vinisharamkumar4181
      @vinisharamkumar4181 6 หลายเดือนก่อน

      The number representation followed is signed 2's complement. So the msb bit represents the sign
      For negative number sign bit is 1 and the remaining bits will be a 2s complete.
      A and B is 16 bit, and fractional value is 8 bit long and integer value is 8 bit long
      1. Convert A440 to binary 1010010001000000
      2. The msb denotes it's a negative number .so take 2s completement of the remaining number.
      3. Be careful while considering the decimal point