FPGA 25 - Shared PS-PL AXI BRAM Application on Zynq SoC FPGA (Verilog)

In this episode, we're building a complete Zynq SoC FPGA application demonstrating a shared AXI BRAM architecture where both the programmable logic (PL) and the processing system (PS) share a 2K by 32-bit BRAM memory and able to exchange data through this shared BRAM buffer.
To test this design, we would initiate writing 32-bit counter data into this shared BRAM from the PL side upon system reset and have a software program on the PS side access and read out the first couple memory locations of this shared BRAM.
Even though the example application is being demonstrated on the MiniZed board, it would run on any board with a slight modification of the selection of the target Zynq SoC FPGA device, the DDR interface and the terminal UART pinout to match the target hardware.
#fpga #zynq #vivado #vitis #embedded #verilog #xilinx
Related Zynq SoC FPGA episodes:
FPGA 29 - Zynq SoC FPGA XADC application to measure on-chip power supply voltages and die temperature
• FPGA 29 - Zynq SoC FPG...
FPGA 27 - Zynq SoC FPGA PL interrupts PS to trigger software execution
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FPGA 26 - Shared PS-PL AXI BRAM Application on Zynq SoC FPGA (VHDL)
• FPGA 26 - Shared PS-PL...
FPGA 20 - Build complete Zynq SoC FPGA application for PYNQ-Z1 with software control of AXI GPIO LEDs
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Recommended prerequisites:
FPGA 1 - Set up AMD Xilinx Vivado/Vitis (free version)
• FPGA 1 - Set up AMD Xi...
FPGA 3 - First Verilog Vivado project for beginners
• FPGA 3 - First Verilog...
FPGA 4 - First VHDL Vivado project for beginners
• FPGA 4 - First VHDL Vi...
FPGA 15 - Xilinx Zynq SoC FPGA Build your first "hello world" program
• FPGA 15 - Xilinx Zynq ...

[@tobiaszoske4552]

nice videos for FPGA beginners !

[@FPGARevolution]

Very glad you find them helpful. Cheers!

[@shravanilakhote7338]

Sir , is it okay to store the data in the bram using .coe file ? and how do you read the contents of the memory without using hardware ? is there any specific tcl command for that or i can read it through simulation ?

[@user-jz4pl1wb4p]

XPAR_AXI_BRAM_CTRL_0_S_AXI_BASEADDR variable is auto generation????

[@SanjanaS-ot9xe]

sir.. can we use this design for zedboard sir? for accessing ddr memory

[@FPGARevolution]

Yes but make sure to select the right Zynq device and let the tool generate drivers

[@mamathan7365]

Pls share the. V file content also

[@FPGARevolution]

Code is all there. Make sure to pay careful attention as it's a short episode, only couple of minutes.

[@aranyagupta8588]

.addra(bram_porta_0_addr[12:2])
kindly let me know why the PART A has [12:2] not [12:0].

[@FPGARevolution]

32-bit addressing example

[@aranyagupta354]

​@@FPGARevolution Can you tell me if I want to store 64-bit data to BRAM memory and print it through UART, In which steps I need to make changes?
I have tried by changing index to 64 bit in both BRAM controller and Block memory and using the following code to print data using UART:
#include
#include "platform.h"
#include "xil_printf.h"
int main ()
{
u64 *address = NULL;
init_platform();
print("BRAM Test successful.
");
address = (u64 *) XPAR_AXI_BRAM_CTRL_0_S_AXI_BASEADDR;
for (u32 i=0; i

[@aranyagupta354]

@@FPGARevolution Can you tell me if I want to store 64-bit data to BRAM memory and print it through UART, In which steps I need to make changes?
I have tried by changing index to 64 bit in both BRAM controller and Block memory and using the following code to print data using UART:
#include
#include "platform.h"
#include "xil_printf.h"
int main ()
{
u64 *address = NULL;
init_platform();
print("BRAM Test successful.
");
address = (u64 *) XPAR_AXI_BRAM_CTRL_0_S_AXI_BASEADDR;
for (u32 i=0; i