FPGA 30 - Zynq SoC FPGA Direct Memory Access (DMA) between PS DDR memory and PL AXI4-Stream FIFO

In this episode, we're building a complete Zynq SoC FPGA application demonstrating direct memory access (DMA) in both directions between the processing system's DDR memory and another block of memory with an AXI4-stream interface residing in the programmable logic fabric.
The application is validated on the pynq-z1 board.
The DMA engine is configured by the C application through the AXI4-Lite interface to initiate DMA-read and DMA-write operations. In DMA-read operation, a block of 16 32-bit incrementing numbers is transferred from the DDR to the AXI4-Stream FIFO data buffer. That block of data from the AXI4-Stream FIFO is then moved back to the DDR at a different memory location through a DMA-write operation. The received data is then read and verified to validate the complete DMA application works as intended.
#fpga #zynq #vivado #vitis #embedded #verilog #xilinx
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Recommended prerequisites:
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FPGA 3 - First Verilog Vivado project for beginners
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FPGA 15 - Xilinx Zynq SoC FPGA Build your first "hello world" program
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[@nikolaykostishen6402]

Thanks for nice tutorial as usual.

[@FPGARevolution]

You're very welcome!

[@jonggeunlim6151]

Nice video

[@user-vj3cx3hj9g]

thanks for this tutorial video

[@mannguyen5781]

hi, i have a question, and I need your assistance. When does DMA stop reading? Many thanks.

[@sw3916]

Hi thanks for the video, dont you need to connect the fixed_io and DDR pins of the Zynq7 block in the PL via the auto connect?

[@edward4061]

Hi thanks for the tutorial. What changes i have to do if i want to send data from PL AXI SPI to PS DDR3 using DMA

[@angelg3986]

Nice video. Do you have another showing how an FPGA on the PCIE bus of a PC can do DMA C2H via PCIE ?

[@user-py6zc5gx3l]

could the design be shared? maybe tcl