FPGA 19 - AMD Xilinx VHDL CORDIC Sine/Cosine generator

A hands-on tutorial on sine/cosine waveform generation using CORDIC algorithm IP through AMD Xilinx Vivado VHDL design flow.
#fpga #vivado #vhdl #xilinx #amd #simulation #trigonometry #dsp

[@FPGARevolution]

This episode gives you a quick snapshot into how sine and cosine waveforms can be generated. For those of you that's working on incorporating this into your own projects, please make sure to look at the DSP episode 24 also as the testbench in that episode has a hook in the phase sweep to properly handle the transition from +pi into -pi region keeping the phase jump constant during the transition. In this episode, the transition only guarantees the rotation to continue in the same direction after the transition cross-over.
th-cam.com/video/5bp4iYJ51qM/w-d-xo.html
Also for those asking for the specific formula for the frequency of the synthesized waveform. The resulting synthesized frequency is a function of the sampling frequency, the phase jump and the phase resolution (total number of steps). The phase resolution is fixed in this IP and the total number of steps is 2*PI or 51,472. The equation for synthesizing the exact frequency is Fout = (phase_jump * sampling_frequency) / 51,472 so plug in your required Fout and tune the two parameters in the numerator accordingly.

[@oliverlabert]

thanks!

[@nikolaykostishen6402]

Nice! Thanks!👍👍👍

[@FPGARevolution]

You're welcome!

[@user-tp8ht3ih2t]

Code is not running

[@user-eo2sw9gb4t]

Hii, nice video, thanks. I change the logic of rst. i made it active low rst I got the glitch at sincos_tvalid after that sincos_tvalid continuously high. why ?
how to calculate the frequency of sin wave. how to achieve sin of different frequency.

[@FPGARevolution]

You're welcome. When you apply your reset sequence, make sure to carefully inspect your logic to make sure it properly handles the control including initial condition and see if any glitch makes sense as a result of that. Regarding frequency of the sine wave, try tuning the sampling frequency and the phase and you will see how the frequency of the sine wave varies accordingly.

[@nashatali6030]

​hi thanks for the video
can you tell me exactly what parameters to change in the code to achieve my desired frequency of the sine wave and is their any equation to use @@FPGARevolution

[@user-eo2sw9gb4t]

Hii, i want to achieve the frequency of sinwave 2khz, how can i achieve it ? further i am passing the output of cordic ip i.e sin to dac. how to control sin value its change very fast due to some value missing at dac output ?
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sincos is
port (
clk : in std_logic;
cos : out std_logic_vector(15 downto 0);
sin : out std_logic_vector(15 downto 0);
sincos_tvalid : out std_logic
);
end entity sincos;
architecture arch of sincos is
constant clk_period : time := 10 ns;
constant PI_POS : signed(15 downto 0) := "0110010010001000";
constant PI_NEG : signed(15 downto 0) := "1001101101111000";
constant phase_inc : integer := 256;
signal rst : std_logic := '1';
signal phase_1 : signed(15 downto 0);
signal phase_tvalid_1 : std_logic;
component cordic_0 is
port (
aclk : in std_logic;
s_axis_phase_tvalid : in std_logic;
s_axis_phase_tdata : in std_logic_vector(15 downto 0);
m_axis_dout_tvalid : out std_logic;
m_axis_dout_tdata : out std_logic_vector(31 downto 0)
);
end component cordic_0;
begin
process(clK)
begin
if rst sin
);
end architecture arch;
@@FPGARevolution

[@FPGARevolution]

You're welcome. Take a look at the pinned comment above.

[@FPGARevolution]

@@user-eo2sw9gb4t If you want to interface the output of your synthesized sampled waveform to the DAC, you need to think about the synchronization or the relationship of the sampling frequency between your DAC and your waveform generation. When would you expect to have a sample from your waveform generation and when would you expect your DAC to grab a sample and output it ...