FPGA 26 - Shared PS-PL AXI BRAM Application on Zynq SoC FPGA (VHDL)

In this episode, we're building the VHDL version of a complete Zynq SoC FPGA application demonstrating a shared AXI BRAM architecture where both the programmable logic (PL) and the processing system (PS) share a 2K by 32-bit BRAM memory and able to exchange data through this shared BRAM buffer.
To test this design, we would initiate writing 32-bit counter data into this shared BRAM from the PL side upon system reset and have a software program on the PS side access and read out the first couple memory locations of this shared BRAM.
Even though the example application is being demonstrated on the MiniZed board, it would run on any board with a slight modification of the selection of the target Zynq SoC FPGA device, the DDR interface and the terminal UART pinout to match the target hardware.
#fpga #zynq #vivado #vitis #embedded #vhdl #xilinx
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FPGA 20 - Build complete Zynq SoC FPGA application for PYNQ-Z1 with software control of AXI GPIO LEDs
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FPGA 3 - First Verilog Vivado project for beginners
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[@nikolaykostishen6402]

Thanks!

[@FPGARevolution]

You're welcome!

[@amitabhxyz]

Savior! Thanks for this. I can't seem to find any decent video on doing this. Also, if you can make a video demonstrating handling streaming data (without FIFO buffer overflows) from PL to PS, that would be great!

[@FPGARevolution]

Take advantage of the later episodes regarding DMA and data acquisition. Cheers!

[@karter972]

Promo>SM