FPGA 28 - The power of mixed-mode clock manager

In this episode, we're going to look at mixed-mode clock manager primitive or MMCM, one of FPGAs' many powerful capabilities.
A mixed-mode clock manager is similar to a phase locked loop or PLL in that both of them can be used to generate multiple clocks with arbitrary defined phase and frequency relationships to a given input clock. But a mixed-mode clock manager has a couple other advanced features such as fine dynamic phase shift and modulated spread spectrum control of generated output clocks.
We're going to demonstrate an example design utilizing a MMCM running on the PYNQ-Z1 board.
In this example design, the FPGA would take in a 125 MHz clock input and use a MMCM to generate 4 output clocks at 10 MHz, 20 MHz, 30 MHz and 40 MHz.
For those of you that don't have access to a handy oscilloscope to probe and validate the clock outputs. The example design also includes a trick to use the 4 on-board LEDs to help with this validation.
#fpga #vivado #verilog #xilinx #pll #clock