Bonus Ask GN(Steve) video for public viewing on the secondary channel -- this one answers a bunch of bike questions from our viewers: th-cam.com/video/Ntl2QlckFIM/w-d-xo.html Get access to our bonus episodes and content on patreon.com/gamersnexus
Not a question but I need to say it. I respect the hell out of what you do, Steve. I can't thank you and the team you've built up enough for your hard work. I've only been following your channel for a year but I've watched each and every one of the videos you publish and they are all dynamite man. I've learned a lot about the industry, hardware, the TH-cam world, YOU, the team, how to approach challenges in your life and work etc etc. I don't think you hear it enough, so from a huge fan: You guys all kick ass and I hope you're having an awesome time in Taiwan.
Question: Would you ever consider doing partnership with manufacturer to create a GN designed case in the same vein as der8auer did? I think community would love this. Then let der8auer do the review on it :-)
I don't think any manufacturers out there is brave enough to try to build a case to their standards. "This fretted gossamer spider-silk dust filter is great with an 88% open surface area but it's a little fragile. I was thinking you could probably chemical vapor deposit a three 10nm layers of corundum on it so that I can't poke a hole in it if I stab it with a screwdriver? That'd be great. I've also come up with this new claw-shaped weave pattern so that IF Snowflake decides to sharpen her claws on it it will legit sharpen them. Can you work that? GREAT!"
@@schumbo8324 Hey fuck it, we all gotta eat and misewell try and make a living out of what you enjoy if you can, automation is the key to that. I wouldn't be too worried about analytics at this point, the US still has friends 😅
They do, but they are price limited. They have much much shorter lifespan than spinning rust and aren't worth enterprise ssd size which typically will be the reason for larger sizes, not consumers
@@mbsnyderc because unless you have fiber gigabyte minimum, an ssd is faster (even with gigabyte a directly connected ssd is faster, with good ssd's being 2-4x the speed)
Where is the cost difference between aluminium and steel cases? How much difference is in the raw material? How much in tooling or other stages of manufacturing? Does the cost difference justify the massive retail price difference or is it mostly just "premium" marketing?
Aluminum is roughly 5x the cost of steel per pound (.35/per pound for steel vs 1.52/lb for aluminum) I don't think the tooling would be any less for a different type of metal.
Aluminum sourced in high quantity for this type of manufacture is usually more expensive by a factor of about 3, and is usually about 20% more expensive to assemble, though assembly costs may be close to parity if no welding is involved.
2 major issues, 1 tax on importing steel is much higher to U.S. and steel is quite a bit heavier, while not an issue for 1-2 cases, but when shipping a container with 1000+ cases, it does become an issue. Besides do you need cases that use steel? Do you find yourself deforming a lot of aluminum cases?
Its funny for a case i prefer steel 100% of the time. its more durable and i have seen many alu cases with screw holes being destroyed. i even filter on it as i refuse to buy or sell a alu case as in my opinion its a matter of when it will fail rather then if. latest case i bought the factory ruined the gpu screw hole and just ripped the threads like happens all the time. thats not happening with metal unless you try hard. same on my 1200 alo road bike the brake just ripped off die to a factory flaw in the mouse screw hole. its a failure waiting to happen. its a weak material.
30:10 Got to admire Linus for him willingly be able to take on such an empire and the risks and rewards for keeping 30+ employees constantly working and making ends meet. The industry overall for content creation has been rough and uncertain and for Linus to go from a guy who filmed unboxings for a side channel for his employer to someone providing a living for 30+ employees is nuts. All the while literally being the face of the channel and subject to scrutiny and stress. Don’t blame him for wanting an exit path eventually.
Question for Overclocker(s): What do you think about nvidia GPU Boost 3.0 and similar auto OCs (Especially CPU auto OC) and do you believe manual overclocking will become more of a niche as these technologies become better?
Feel free to reformat my question. English is not my first language. Main point I'm trying to get to: Will we ever get good CPU auto overclocking? Want to know as it was interesting to see SiliconLottery not carry AMD zen 2 CPUs.
well as a general idea you will almost always be able to push manual overclocking that tiny bit more imo but it's practically already at the point where the difference is negligible
Linked to this: why does intel, while laggin behind in performance, still leaves more performance on the table than AMD? I find it similar with Nvidia GPU (before Vega) they overclock better than AMD cards. I rarely see RX480 / 580 getting more than 100mhz on memory while on Nvidia cards usually i see around 300mhz . All this from an AMD fan but system builder point of view.
It can get rather difficult. The PCBs for motherboards can get anywhere from 8 to 40 layers. The problem becomes making sure that when you do your routing you follow the documentation from the IC manufacturers. For example, gigabit ethernet controllers require at least four layers, and in some of those layers certain wires need to be paired together so there isn't any cross talk on those traces. RAM alone has like 258 odd lanes that need to feed into the cpu socket and be impedance matched. The process for designing them starts with listing out all the functions you want your pcb to have and do. Then you start picking the integrated circuits that will allow you to achieve the desired functions. You check the documentation to make sure the ICs perform to the specifications you need. You make sure that they have the right communication protocols. For example, is it using I2C, SPI, etc... to communicate. You have to make sure everything can transmit data to what it needs to. Then you have to look at interference. For example, you may not want to put a switching voltage regulator net to a wifi IC as switching reg release a lot of EMI noise and this could really mess up your wifi signal strength. Once you have figured out the nitty gritty with com protocols, physicial limitations, you build a schematic and connect everything together. You add all the supporting filtering capacitors, decoupling capacitors, resistors needed for IC regulation/feedback loops. RAM especially needs a lot of decoupling caps because the memory IC's they use are so damn sensitive. Not to mention everything has a certain voltage that it is happy with, typically 1.8v ,3.3v ,5v ,12v. You need to route all the power traces from the PSU so that each chip receives it's necessary power. If the power supply doesn't have it, then you need to make a voltage divider that converts it to what you want with resistors. Then once your schematic is done you do an electrical design rule check. Depending on your PCB software (Altium, Eagle, Mentor, KiCAD, etc..) you are able to test for shorts (faults) you are able to make sure your inputs go into outputs and vice verse, you make sure that you have no stray wires that aren't connected. Then once you do that you make sure you have your footprint library up to date of all the ICs that you use. All of them have different package sizes and when the PCB is milled out then acid washed it needs to put the pads for the ICs in the right places with the right tolerances. Once you have all your footprints you start laying out the pcb placing the components in different areas based on the design. You know that there is going to be a lot of IO near the back pannel, so you know you are going to want to put your various connectors there. You once you have everything placed. You generally on intricate boards will make one side a power plane and one side a ground plane. Then you need to make sure that the ground plane is either clean or dirty depending on whether you have really noisy signals grounding to it. then as we go into the core of a PCB, typically FR4 we route all of the traces which are represented on the schematic. Then once done you do another design rule check but this time for the physical board. Once done you export the gerber files which are files that tell the fab shop where the traces, vias and various pads are on the board so it can machine it or acid-wash it. Typically everything these days they choose ENiG gold coating because it doesn't corrode like lead or tin will over time. Typically when you send it to get the board fab'd you do what is called turn key. So the fab house not only makes the pcb, they also create a solder stencil for solder paste, and use a pick n place machine to build the board, then run it through an oven to solder everything at once that doesn't have plastic. And that's how it's typically how it's done, mileage will vary on depending on what company you work for.
@@christopherjohnson4362 fantastic answer. I figured with the massive numbers of traces involved there'd be more automation on laying out traces for basic ICs and such, then people would go back over it again to make sure there wouldn't be too much interference, but I suppose the way you described it makes more sense. Thanks!
Some of what he mentions is more related to hobby level boards. And he forgot some things like breaking out BGAs. Modern ICs have connections all along the bottom surface rather than just the edge. These internal pads have to be routed out. The more of them there are, the more difficult it is. Prime example being the CPU socket. That alone is a significant factor in the number of layers you're going to use. I have never designed anything that complex, but I would probably start by placing the important components and features. Whether it's for mechanical, thermal or electrical reasons. Some will have a fixed position (like mounting holes or PCIe slots where it's prescribed by standard), some will be more flexible but you have a general idea (like socket, DIMM slots, rear IO or internal SATA connectors). Then I would break out at least the socket. Sooner or later, you'll have to breakout everything so you might just as well. Then I would route the high speed traces like PCIe and RAM. Those are difficult. There are plenty of rules and best practices you need to keep in mind. That's why you do them first when you have a clean slate. Then I would probably look into power supply for power hungry chips. You already did some of that as part of the breakout as you want to put decoupling capacitors as close as possible. That's why they're often found right on the other side of the board. On a complex, multi-layer board, you might end up with multiple ground and power planes. First layer typically has high speed traces on it (there might be a ground plane beneath it). If you're interested, you can find guidelines online for laying high speed traces. You'll learn about impedance matching, guard traces, layup. I don't know about using voltage dividers to supply voltages which are not available from the PS; generally, you typically use local voltage regulators. Then you can start on the lower speed stuff. If there is any analog circuitry, it definitely needs a priority (mixing analog with digital requires forethought). Generally speaking, autorouters don't do a very good job. I can't speak for the top end packages which are eye-wateringly expensive (you really have to do it for living). On the other hand, there can be a load of trivial traces. I wouldn't expect a motherboard designer to hand route everything, not at all. And you can use them selectively. So you could try autorouting the high speed lanes first. The expensive packages have tools that simplify things like length matching for RAM. They also have tools for things like signal integrity. So you can look for potential problems even before making a prototype. Generally, you proceed from the critical and difficult to the mundane. Everything is relative. If you do it for a living, it's routine. Currently, the PCIe 4.0 might be a bit of a headache because it's fairly new. But they'll figure it out. If you're a hobbyist, it's practically impossibly difficult. You don't have the experience, the software that would make it easier is very expensive and the hardware to test your work is very expensive as well. Perhaps a better question would be how many man-hours it takes an experienced designer to design/ layout a board with something like X570. And of course, you can ask specifically about the tools they use - like how much they rely on autorouting.
A question for GN: Do you, Steve, answer the "Ask GN" questions by yourself, or do you sit down with the team to make sure you have the whole team's opinion on the question?
@@hotaru25189 Iows, pride and probably because everyone must try to get everyone else to license and use their ( probably proprietary ) setup. So pride and greed, classics.
I mean really, why can't they just pin out modular cables like pass-through extension cables? Nobody needs to use anyone else's format. They are just complying with the connector specs for the different sockets on the board.
It's because PSU vendors want to ensure that you buy *thier* cables and nobody else's... the Minifit JR connector type is basically a defacto standard and if anything they are only making minor modifications so that it doesn't match other vendors. In short there is no technical or engineering reason why they can't they just don't because money and or liability if you use another vendor's cables.
@@Wingnut353 "Liability" ha! They may use that as an excuse for why they do it, but it isn't for liability. Cable extensions, adapters, sleeving your own cables...once the angry pixies leave the metal box, all bets are off. Besides which, you could easily argue that not standardizing the pin layout on those cables *and* removing the color coding on the wires makes the product less safe.
On the question towards the end.... 30min mark, very interesting and similar boat with our business! It's hard juggling, maintaining and running a small business!! Congrats!!!
I hope GN asks him this question! BTW I've overclocked an iMac G3 by resoldering a resistor that controls the CPU multiplier (350 to 400MHz), and the ATI GPU could also be overclocked, though that was simply done via software.
*overclocks microcontroller embedded in....* you finish the sentence :D alot of micros are super easy to OC by as much as 25% too... since they are often designed with really good safety margins. Actually MCU overclocking competitions would be really fun and cheap to get into... kind of like the pinewood derby of OCing. Rules could be something like no heatsinks, no non standard copper boards 1oz copper only, any oscilator you like, any passive components you like and a specific MCU.
Re: L2/L3: When reading data the CPUs have to first check with every other CPUs if they have a modified copy of the data in their cache and grab ownership of that cache line. Especially with the awesome number of cores we're getting today things are getting very complicated tuning for all the different workloads: games, browsing, photoshop, 3D rendering/video edit/encoding, AI learning, etc. The L2 size is a compromise in part for the circuitry cost & timing cost of L1/L2 caches checking/answering "No, I don't have your data, leave me alone." Larger cache means more to check and more to exchange out. Having a smaller L2 causes the data to end up back in L3 sooner which counter-intuitively a smaller L2 can increase performance in multi-threaded workloads because by the time another CPU wants that data there's a better chance it's already in the global/shared L3 rather than still in the inaccessible (quickly) other-CPU's local L2. A CPU can access it's L2 faster than it's L3, but *ALL THE OTHER CPUs* can access the L3 faster than a different CPU's L2 or L1. Multi-core changes the sweet-spot for cache sizes and single-threaded/single-CPU workloads aren't penalised too much by hitting the L3, when no other CPU is working it has the huge L3 all to itself but still can't use other CPU's L2 which is then a lot of wasted silicon.
depend on how many ways on l2-l3 cache ways and its function example victim cache on l3 ... way better than flash ur pipe line and wait few clock retrieving data from ram... so its depen on uarch and how good its branch prediction
@Science! This still holds true on single chip designs, But its quite a similar problem to NUMA. Adding to @Stephane you also have a Problemn with associativity and not just the MESI Protocol. To properly use a cache you would like to know which bits and bytes are the oldest and use a LRU strategy. Which gets increasingly complex with an increase in associativity, tho an increase in associativity often leads to better Performance in most applications. So 512Kb L2 cache is considered the sweet spot for performance in most applications (depending on architecture of course).
@ufster81 That's actually how Bulldozer was designed to work more or less. The modules shared FPUs and L3, the idea being that they would take turns and share the workload. The APUs sacrificed the L3 cache for GPU cores. Bulldozer's main problem was that most software wasn't optimized for that sort of workflow, which lead to a lot of congestion, especially in FPU heavy tasks like gaming. The CELL works in a similar manner, just with more complexity in how it can delegate tasks. It could even handle GPU functions.
@Science! Single chip Intels have the same challenges: The L2 is still per-core, while the L3 is shared. So a single-core/single-thread workload can only fill it's own L2 (and the L3). In that workload on a 4-core that causes 3/4 of the L2 caches to be unused, on a 18-cores i9 that means 94% of the L2 caches goes unused for single-core tasks. Putting more silicon area into L3 than L2s means less wasted silicon space. And a multi-thread, multi-core workloads still wants more shared L3 so all the CPUs can share and pass the data around more efficiently without hitting RAM's comparatively enormous latency.
Is there any prospect for x86 designers to make assymetric core designs, like ARM SoCs? Eg. Having a (few) single thread focussed cores with bigger caches and better IPC, with clusters of multithread cores centered around the L3? I don't know a lot about Arm's μarch, so I imagine accessing the cache is different but I'm finna believe
So, I keep hearing about TSMC, but a while ago I remember reading about an agreement between AMD and Global Foundry. Where has GF gone now that all this new architectures are produced using TSMC nodes?
Global Foundries still makes the IO Dies for Zen chips because theyre 12nm instead of 7nm. Global foundries killed their own 7nm R&D and manufacturing when they did a large restructuring in the company, during this they lost AMD, so therefore I dont think they make 7nm chips, specifically focusing on 12 and 14nm in emerging markets
IIRC GloFo wanted to go for mass market rather than bleeding edge, even though they sued TSMC over 7nm technology for some reason. I do believe that AMD still has a wafer agreement with GloFo, and they're fulfilling that agreement through the manufacturing of the IO dies. I noticed that the 7nm Ryzen parts have two locations specified for where it was diffused, and I believe the Malaysian plant is GloFo and Taiwan obviously being TSMC. This is all from my dodgy memory, and I cba to re-look it up atm.
TSMC. AMD spent a lot of money I believe 2 years ago to get out of the contract with GloFo. Now GloFo still makes almost everything for AMD except for the 7nm stuff. I think AMD still has to buy enough chips from GloFo to not be in violation of the agreement, but now AMD can use other Fabs as well and no longer limited to GloFo. But then again this is likely the reason why AMD is still making Polaris cards and rereleasing Zen processors like 1600af
The single use bags are great to hear about. It's crazy to see so many bigger companies just ignore the impact of their waste. You guys go out of your way to ensure good practice in every project I see. Thanks GN team
In regards to L2 cache sizes. L2 is typically around 128-512 KB per core. This might not seem gigantic compared to the handful of MB or more of L3 that most CPUs have on offer, but L3 serves a fairly different role compared to L2 and L1. Now the role of cache in a CPU is typically quoted as being used for "reducing latency", why this isn't correct we will get into. Latency is honestly not a big problem for a CPU, we can generally fix the problem of latency by simply decoding instructions earlier, and putting them into a queue. This gives us the option to prefetch data many cycles before it is going to be executed. This though means that we also need to prefetch both sides of a branch in our program, effectively doubling our bandwidth requirement from that point on, and any additional branches down the line will just as well increase our bandwidth requirements. (This is part of the branching problem, and branch prediction can partly fix this issue too, but in case of a miss predict a lot of architecture implementations still prefetch at least the first branch regardless.) This can very quickly lead to rather exorbitant bandwidth requirements. So the frankly pathetic bandwidth over to main memory will not be sufficient (yes, DDR4 with its 20+ GB/s is rather lackluster as far as even a single core is concerned). This is why we add cache. With caching we don't need to fetch data from main memory, but can instead fetch it from cache if it is in the cache. This though obviously introduces a new problem. How many cycles does it take to check if the data is in cache? Well, the answer is, it depends on how much cache you have. L1 for an example is very small, and therefor generally fairly easy to check all its content. Now L1 is typically extremely parallel in how it searches for cached content, typically able to handle 10+ of cache look-ups every cycle, meaning that it is extremely fast, but also extremely expensive. (64KB of SRAM needs about 2 million transistors, L1 in most CPUs can have over twice that amount of transistors...) L2, is substantially larger, and generally won't get talked to as often, after all, L2 is only contacted if L1 has a cache miss (and that is typically less than 5% of all cache look-ups that L1 handles.). (in some architectures L2 is sometimes called on regardless, for cache coherence reasons....) L2 isn't as busy as L1, despite typically having 2-4 cores poking it, and we have lots of time, we can instead focus on making it more cost effective instead of being able to respond instantly. L3 is the least busy cache level, though since you typically have many cores in a CPU, L3 tends to be more busy then L2 in some CPUs. But When you reach L3, your core is most likely stalling when you finally get the data... And if you have a cache miss, you better hope that the kernel switches thread, since now you are going to main RAM over a comparably slow, high latency connection.... (Just to paint a picture of how slow it is, access latency for DDR4 is around 5-15ns. Or from a 3.8GHz CPU core's perspective, 19-57 cycles, or around 95-750 instructions. (Thankfully DDR4 will read you back some 64 bits of data in that time, while a well designed L1 could have provided those 750 instructions with typically around 64 bits of data each without much hassle. Ie well over 100x the bandwidth of DDR4. Not to mention that the memory bus might be preoccupied, so your call has to wait in line for a "few" more cycles...)) Making L2 larger would risk stalling each time we fetch data from L2. This isn't ideal, since we would be wasting time. Making L3 larger on the other hand is a very different story. L3 serves the purpose of making sure that we don't instantly bottleneck on the frankly pathetic bandwidth that the main memory buses have on offer. That L3 gets a bit slow is less important, the only constraint here is how fancy our caching system is, and how much resources we wish to spend on SRAM. So why not prefetch even earlier? Surely that would fix the stalling issue? Well, it fixes stalling, but now you risk having more branches, and thereby higher bandwidth requirements, and thereby making L1 more expensive. Since each new branch means that we need to decode an additional instruction during the same cycle. And together with out of order execution that already pushes us to decode 10+ instructions per cycle just to keep up with execution. Each additional branch would effectively require us to prefetch another 10+ instructions per cycle, so we don't want to risk decoding too many branches, since then we have a ton of instructions to handle. Each instruction having 2 or more variables, thankfully, a lot of these variables will not even result in L1 cache look-ups, since it will just use various registers instead. But it isn't unfair to state that 1 out of 5 instruction calls results in a cache look-up. (this though varies greatly depending on the code being executed. One can have no cache look-ups in 500+ cycles, or have them every cycle. So it can vary a lot.) In The End: L2 size is practically dictated by how many cycles ahead of execution one can prefetch, and how large of an array one can effectively index and fetch from inside that amount of time. And how many cycles that is, is typically determined by how many instructions one can expect per cycle, + any additional overhead due to branches. And that in turn is dictated by how many cache look-ups L1 can handle per cycle. (And how good one's instruction decoder is) In short, larger and more parallel L1 and faster decoder = possibility for larger L2. (But this comes at a cost, and a lot of applications wouldn't noticeably benefit from it.) Increasing L3 cache tends to have more noticeable gains, since most stuff that is too large for L2 tends to instead be bottle necked by main RAM. Though one needs a lot of L3 to make a major change here. But if the dataset of an application is small enough to fit in L3, then the application can have little to no need going out to main RAM. (Though, L3 only partly supplements main memory bandwidth, but it doesn't increase actual memory bandwidth. To increase actual bandwidth, we need more memory channels.) Also, I should point out that I am greatly oversimplifying things here, this is a youtube comment, not an in depth article on system considerations regarding L2 sizing.
@@Leap623 No problem, always nice to see that people find my walls of text as informative. Although, I could likely cut out a few sentences here and there and condense it all down a bit. At least I didn't waffle away on the topic of how all this gets far more maddening with cache coherence checking between NUMA nodes... And the various methods of partly resolving such issues.
@@todayonthebench Would there then be the possibility of an L4 caching system that could supplement L3 caching, thus reducing demand for main memory being demanded by the system?
@@XRioteerXBoyX First of, main memory doesn't get damaged from just using it. The problem is that main memory buses tends to be extremely slow compared to what a bunch of cores actually need. So we just get the computer equivalent of traffic congestion. In regards to L4, some systems do use it. L4 is though a rare sight since it doesn't really make much sense. First off, L4 would need to be bigger than the already huge L3 for it to be effective, making it rather expensive. Unless one uses DRAM for it. (This works since we are trying to solve bandwidth, not latency.) The next problem is that it needs somewhere to be. Preferably on the CPU chip carrier as to not occupy pins on the socket. (though one can make it a "complicated" memory controller out on the motherboard. That then in turn talks to main memory.) Though, L4 has the next bigger problem. And that is, L3 can already be arbitrarily huge, L3 can already use tens of GBs of HBM memory if one so desires, since when we reach L3, the core should be at the verge of stalling regardless. So as long as L3 cache indexing and fetching the contents from its memory is offering more bandwidth than the main memory buses, and preferably has lower latency than traveling through the memory controller queue, out to main memory, and fetching the contents there, and getting back again. Then L3 has no actual limits to how large it can be, rendering L4 rather pointless. In the end, it has proven cheaper and more effective to just fix the actual bottleneck, ie give the processor more memory buses. As an example, all CPUs used to only have 1 memory channel. These days, a low end CPU has 2.(LGA1155-LGA1151, AM4, AM3, etc all uses 2 channels) Higher performance system usually have 4. (LGA2011, LGA2066, Threadripper) In the server space, LGA3647 has 6 channels, Epyc has 8, and Intel Scalable has 12.
"Do one thing really, really well." - Steam Whistle brewing. :) You are kind of in a unique position among tech content creators - you balance being an effective media outlet with being more technical than most other popular channels without being super-technical. I think that's your sweet spot. I watch your channel to learn. I also appreciate your environmental responsibility. Oh, and your seeming disdain for companies that just puke RGB on products. :)
Question for overclockers: I've heard that increasing (GPU) memory frequency can decrease performance because the memory ends up having to correct more errors. How does this process work at a more in-depth level? How does the hardware know there's an error, and how does it know how to correct it? Are there any ways to log these corrections in software?
very interesting because on Polaris there is an actual error counter but on some tests like firestrike i can see no artifacts but i see mem errors show up in hwinfo, while in TimeSpy i see light spots in green and white but no memory errors show up!
You know there are errors when artefacts starts showing on ur screen, which you can count with your eyes. If you mean DRAM then run a stress test with MemTest86
Are you talking about ecc memory? This is the only type that will correct errors, by including a 9th bit they correct based on whether a bit flips or not, as a very basic explanation. Standard ddr4, overclocked or not will not error correct.
I actually had that happen today - I boosted my GPU memory frequency 300mhz and the Cinebench scores dropped from 4826 to 4746 - ran test multiple times... CPU is 3700X with the 2060 KO Ultra GPU and 32GB 3600 DDR4 RAM
I have a G5 laser mouse that is 14 years old and still works great. I finally upgraded last year when I built my new machine back in July. I'm now using a G-Pro Wireless.
Meanwhile I've found that they added planned obsolescence in the G403. The scroll wheel is built such that after enough middle-clicking, the scroll wheel will break. That's because the part of the axle that's responsible for actuating the scrolling itself, is very thin and molded onto the rest of the scroll wheel very awkwardly.
I have a G500 and G500s (bought the S because the left click button started to wear out after about 10 years where it either double-clicks, or doesn't click instead of working properly). Neither are in daily use anymore but they're still one of the most comfortable mouse size/shape designs I've ever used.
I had G5 for 1 to 2 years it was a great mouse but died. Then moved on to MX518 and the same thing happen. Guess what now I am no longer a Logitech customer.
question for overclockers: cpu deterioration is caused by voltage or heat subsequent by higher voltage? if it’s heat, can the deterioration be stop with exotic coolers?
"Call it lazyness if you want" I do want, and I do call it lazyness. Optimisation is the hidden art of software development that is slowly being lost to time
Fortunately consoles will never let it die out. There is no opportunity for devs to fuck off on optimization for a static piece of hardware that wont change for ~5 years.
@@oscarbanana6159 where have you been? Games are reaching the 20gig range for consoles, and broken as hell on release. Optimization and compression have not been a priority for years on consoles.
@@calebb7012 Storage is cheap compared to processing power. Compression use less storage, bug take more processing power to uncompress in real time. To me, they can go as big as they want as long as it run smooth.
Been following you for years now. This video, after the last 3 topics you and your team gained so much more respect from me. Keep up the mood and the great content!
I rarely comment on this channel videos.. Cause it's already super high quality.. but I really really appreciate the clear answer on 30:10 , his short answer is Quality Over Quantity + extra busy hours Rarely you see people prefer extra work to maintain the highest quality they can achieve, I like people who're loyal to their work
At 28:56 is why I love and respect GN. Quality is in short supply. And yes, automate the hell out of everything. This is a big part of what i try to do.
Anthony F. Like an otaku? As you can tell by every platform that’s ever had a “RadicalxEdward” all being me (and many of the ‘Radical Edward’ and ‘RadicalEdward’ ones too) I’ve been big into anime and japan since I was a little kid, been all over 4chan, tor, the onion, Reddit, social media, etc and have never in my life come across the term “weeb”
I'm super surprised at GN's environmental concern (over multiple videos) and I gotta say it's so good to see that you guys give a damn. And I feel like it's not just fake greenwashing. As you said, the single use plastic bags could have stayed the same and nobody else would have mentioned it.
Steve, love your sedated ethical approach, retooling to remove single use plastic is 100% commendable, as is the fact you have not jump on the ' look how environmentally friendly we are' bandwagon like some others out there. 🌳🌍🌲
Best Buy employees don't know much about anything. During my interview there for the computer department, I had to explain the certification scale of PSU's. And also what a PSU is. And note that these were the department supervisors. This happened at 2 stores. Lol. Then they told me I'm not a good fit.
you knew too much. Occasionally for a laugh I'll ask their computer area people questions just to see what comes out; it seems like their training is primarily covering popular brand names, which aisle various parts are on, and trying to sell extended warranty services. They've always been friendly to me, but I knew more about PC building and troubleshooting as a kid in the Windows 95 era (heavily due to breaking the family PCs so many times) than these poor Best Buy / Geek Squad kids are taught.
They had a great roll model going with price match and having the new Ryzen cpu's on the shelves as to evolve into a Micro Center type store .. because there stores are located close to all major collages in my area but just to dumb to see it and move on it as to scale back the laptop overkill area and open up custom build like the old (Comp USA) early days .
I know of one Best Buy where the IT manager is a former black hat with 160 IQ and a MS in programming... I think it's more likely that they either thought you were slumming for a temp job and they wanted someone long term...or maybe that during your lecture on PSUs, they decided that you'd confuse customers and rub them the wrong way with your holier-than-thou attitude.
I was thinking maybe the 1600AF exist as a another way to fulfill the wafer supply agreement at Global Foundry. Because they get the I/O dies from them too for Ryzen 3000.
There are primarily three ways to increase GPU load: 1. Improved physics, this is mostly CPU, but technically, ray tracing is part of physics (of light). So some aspects obviously can be handled by GPU 2. Improved assets, simply put, more polygon to handle. 3. Decreased optimization. The first two cost money, the last saves money. So even if the cost of developing a game holds the same (i.e. not cutting corner in terms of decreasing cost), there is a path to quite a lot of increase in hardware demand on highest settings, until they cut optimization completely and spend all that money into assets. Beyond that, it would start to cost more money to make a more demanding game, not less. At the same time, the software for constructing/generating the assets are also improving overtime. So the same quality asset will cost less and less to make, in other words, for the same money, you will get better and better assets. So in a way, it will also be an arms race between hardware development and those asset creation tools.
L2 cache input: In a course at university we were told that for all cache (at least in die) there is a tradeoff between latency and capacity. This relates to the fact that the larger capacity increases physical size, meaning data has to travel further, (dis)charge more capacity and potentially go through more circuit which takes longer (and consume more energy). To mitigate the impact of a low capacity while retaining low latency more levels are added as you would need to fetch this data more rarely (which is why it is located in the higher levels of cache) i.e. has less overall impact while still being significantly better than RAM (which can be seen as cache for your main storage).
29:58 "If I can't do it really well [...] then I don't do it." Thanks for addressing my question. I'm still disappointed I couldn't prod GN into doing something with SFF again, but your small team is working on many things so there's a lot on their plate already. I saw your list of pitfalls for CPU cooler testing and for your own sanity I don't recommend being that rigorous with absolutely everything. I mean, you didn't test thermals for the Cute Pet case since that was more focused on the novelty and build quality. Perhaps I just need to find an SFF case under 20 liters shaped like a cat or with a waifu printed on the side and boom, we got some SFF content again! Joking aside, Steve laid it all out clearly and even said "Sorry" at one point so although I really want SFF content I can't really be mad about it.
26:28 I do have an issue with single use plastic bags, but if they’re resealable plastic ziplocks of a unique set of dimensions I tend to keep them , especially if they hold parts for organization.
But really unless you know why you need it you just don't. No gaming doesn't count. A 3600X and especially a 3700x and a 9700K has more than enough cores for gaming and office work.I laugh at those with a 9900K even though I own one (I do hyper-v virtualization with 8 virtual machines with Intel RST raid on 4 ssds is my use case when not gaming)
Thank you Steve for not going super big. We all know what happened to small-medium youtubers when they decided to go super big.. not gonna call names but.. let's just say in most cases their content quality dropped significantly due to them trying to approach a more wide audience. Laziness isn't wanting to stay at a small-enthusiast level, laziness is only reading specs and getting easy views likes most HW channels out there that do 1/10th of the work you do ;)
A good guy. Excellent content and a good crew. Steve and Wendell over at level1 are at the top of their respective games and who's word/opinion you can trust.
Question 1: Is overclocking worth it for normal day to day usage? Question 2: Why is the left side numpad on keyboards (EDIT) not more common? There is a demand for it.
Regarding graphics performance: Increasing resolution and framerate is not some artificial inflation of hardware requirements, it's a very visible improvement in image quality and the experience as a whole. It's just as important as (for example) getting better textures ingame. Speaking of textures: Scanning real objects is a thing and plenty of companies are working on implementing it in broad scale. It'll look awesome, but you can expect hardware requirements to match.
Depends on chipset, but bclk overclocking will overclock everything, including chipset, often causing instability. Old chipsets you could oc, but would need active cooling
There is the BCLK thing which is typically 100Mhz and that’s how you get your multiplier for CPU where 50 is 5000Mhz. It’s possible to manipulate that 100Mhz base value but it has very little headroom and can brick things if you push it so I would basically tell you don’t bother.
AU Optronics is in Taiwan. Would like to know if it is them keeping monitor prices high via panel cost or manufacturers. TV's are catching up and monitor prices don't seem to be decreasing as fast.
L3 Cache growth vs stagnant L2 size. Another angle, because some operating systems (Windows) lack core per thread consistency, threads tend to bounce around cores. placing the data in cache not attached to the core the OS moved the thread too. with larger L3, that increases the chance the data is still in a cache level accessible by the thread as it's bounced around the CPU like musical chairs, instead of an L2 or L1 that has access limits from cores it's not attached to. Steve's point on latency vs size is the other angle, and a very solid one.
On that last Q, I bet y'all could get that Beve Sturk guy. He seems knowledgeable. I don't have any Qs, but keep up the solid content and have safe travels!
Unfunk: If you read this. The reason for the L2 vs L2 discrepancy is that most caches are what they call cache inclusive. What this means is that if you have something in L1 cache it is also in L2 and also in L3. If you do some mental gymnastics you can quickly figure out that if you had a 1mb L1 with a 1mb L2 and a 1 mb L3 that you would have 1mb of usable cache. The best arrangement is to have the last level cache be the biggest and the L1/L2 be as small as possible. The next thing is that as that size of a cache increases so does the latency. So you don't wont your L2 to be so small as to put everything into the higher latency L3 cache. That balance has lead to 512k being the go to for quite a while. AMD up until Ryzen used a cache exclusive design meaning data was not replicated this allowed AMD to have 512kb cache with the first Athlon 64's.
For some reason I hate the hole "doesn't overclock as well" thing. IMO that should be a good thing that the company knows what chips they have and how to bin and market them. If a chip overclocks well that would mean they have a chip that is good but they need to make artificial market separation or, they haven't put the RND into understanding the chips they have made so they just stick them in whatever box fits close enough. That might even be a good ish question for chip manufacturers if you talk to any of them. How do they go about binning and sorting chips? We seem to be stuck in the i3, i5, i7 sorta thing for ages now. eg. low, medium, high... Office, peasant, GAM3R!...
I disagree that "doesn't overclock well" isn't bad. It's a good benchmark to understand the quality of silicon you just bought. Heavy binning hurts the consumer because it's the manufacturer nickel and diming you for maximum profit margin SKUs. Not even hitting claimed speeds under overclock cooling and voltage straight up tells you the silicon left behind from binning is low quality, let alone adequate for it's spec. If you can't even get good 3900s to reviewers that tells you how hard TR is eating up all the good silicon. I would far rather have a 9900k from before they started binning away the best silicon to the KS. AMD's entire stack is binned, they already said so. While they still perform well to cost, you get the feeling you're using leftovers for the middle of the stack and the whole reason 3950 and up perform so amazingly but are rare. They have a lot of high tier SKUs to fill so you effectively have zero chance to get a golden sample without paying for it. With the likes of the KS and AMD upper stack, it's no longer "you get what you pay for" it's now "you're gonna pay for what you get". AKA silicon lottery doesn't exist anymore. You're guaranteed to lose.
Man that talk at 23:28 Is some real damn Tawk. Everything is made to break/breakdown after a certain amount of given time. I have a fan from the 50's that's been in the family for so long. Still going as purchased,mean while some new ones have had trouble/replaced.
Question: Most cases I've used/seen have very little space behind the motherboard for cable management. A SATA power connector jammed back there seems like it'll snap off for example which, depending on where your drive mount is and how long the power cable is sometimes needs to be set back there. PSU shrouds have made this a bit better but: Why don't case manufacturers expand the width of cases a bit to give some more room for cable management? I'd love to see 1/2" to and 1" of extra space but any extra space would help.
Questions for tsmc.1. As we see more ARM based products including Ampere Altra at 80 core and Apple developing their based laptop/ipad cpus how long do you see x86 architecture continuing into the future? 2. How does tsmc plan to resolve quantum effects in future products below 5nm?
A question about PCBs and chips : How does the clock you set via software or bios translate to the "physical" clock? How does it get generated on the GPU/CPU physically (like the multipliers and alike)?
Question for Manufacturing: Is there any likelihood of seeing 3.5" format SSD's in order to immensely increase storage capabilities; particularly for the enterprise segment?
GAMERS NEXUS: My question for engineers is why haven't we seen actual, real improvements of the hardware for CPU's? Now I know this sounds absurd, however, I've been able to get 5.3ghz since the days of x58 at about 1.478v, in fact, I'm still using it at 4.6ghz 12 years later at 1.372v. As a result, my 12 year old comp has better single core performance than the ryzen 2700x, and since most things still dont fully utilize more cores in the gaming world, 6 cores at 4.6 vs 8 at 4.2 ends up being almost identical as well--literally the only thing holding back the performance is pcie2 vs 3/4, so its a physical bottleneck not allowing me to use anything higher than essentially a 1660S in it vs my 2080ti (which even then, doesn't fully saturate pcie3). So its basically that and what... Shadows of the Tomb Raider and Assassins Creed are where, 12 years later, it actually matters? For perspective: GPU'S in the same time have gone from roughly 8800gtx to the 2080ti. Why has there been such a stagnation on the actual performance CPU side when the GPU performance uptick has been incredible? Why are they focusing on smaller and smaller and more expensive to fabricate architecture vs say... 10ghz? If not 10ghz and more cores, why hasn't multicore been properly supported/leveraged when the technology is basically as old as I am at this point? I'd be much more interested in 10ghz or core counts beyond 1-6 being leveraged properly than going from 32nm to 7nm and getting essentially the same performance, except, perhaps, per watt (60-90w 3700x vs 80-130w 12 yo Xeon [18 vs 22 cents p/10hrs]).
The simple answer is that the chemistry of what constitutes a transistor has not changed. The energy level to move electrons to switch a transistor is set at the atomic level by the atoms involved - and has nothing to do with the size of the transistor. The efficiencies in design of a transistor in terms of size and power can only approach the electronic excitation energy levels. So basically speeds of silicon P/N transistors have an upper limit which we are basically at, and making them smaller in terms of nanometers sizes for the junctions, isn't going to change that. Over the years overhead to get close to the energy levels have been removed. However... they are still making the transistors physically smaller, so more on each chip, and less power to switch them. Hence performance can increase by making as many things 'parallelised' as possible. CPUs can only go parallel by adding cores/threads. GPU's however do set tasks, almost down to set task per pixel per polygon/pixel/whatever. Hence they can be made in huge parallel groups. So for example a 2080 down to a 2060 mostly have the same actual clock speeds, just the 2080 has way more cores. And we are talking hundreds /thouands of shader cores, mapping units, more tensor cores, etc. etc. etc. GPUs can probably keep growing to the point where the core count approaches the pixel count without the need for transistors to get faster.
The two main issues with CPUs is two-fold: *Much if not most* of the performance optimization that *can* be done with CPU architecture *has* been done. There are 1000's of tiny little optimizations that go into making the pittance additional IPC gains we get these days. That's the main reason why companies have stopped trying to go much faster as well: a good chunk of the die space in a modern CPU is dedicated to error detection/correction. The faster you go, the more of the die you have to dedicate to it, and the lower your yield per wafer. That's why AMD and even Intel have been trying to get companies to optimize for larger core counts. Even now, they're relying on speculative execution, which continually shows serious security problems (like the exploit showed for AMD Bulldozer and newer I caught in my news feed today). Nobody'd be doing that if they had other ways of speeding things up. Power consumption is now a major selling point, so companies have been encouraged (for battery life reasons in laptops/phones, and Cost/Environmental reasons in Server applications), so neither Intel or AMD have taken the 'eh, throw wattage at it'. And the issue with Silicon is, you can only do that so much anyway, even with a phase-change cooler or LN2 GPUs have gone through leaps and bounds because the GPU's workload can be parallelized far more then the CPU's, so increases in the processing power of each Cuda core/Compute unit is also met with simply having more of them, a LOT more, and more efficient parallelizing circuitry to spread the load better.
remember kids, IPC isn't real and every application is optimized for low thread counts The fact is that Intel pushed the desktop 4c8t mantra for so long it locked desktop software into a sinkhole of singlethreadedness, and the past 3&1/2 years of ryzen has only just begun to break the stranglehold. Clock rates for silicon won't get much higher without some insane breakthrough on a physical chem level, and IPC gains will only go so far. The far future of silicon lies in heavy multithreading and increasing power efficiency/transistor density to achieve mondo coars on the desktop.
"As a result, my 12 year old comp has better single core performance than the ryzen 2700x" Nope. Newer architectures execute more instructions *per clock cycle*. They call this idea "IPC uplift" (instructions per clock). If it worked the way you are thinking, PrescHOT processors would still rule the roost in single threaded performance.
Right, so Intel is faster, in number of workloads or specifically games. Important to remember Spectre and Meltdown, branch prediction, and AVX512 among other things. AMD chose a more reliable part with fewer fault points. They haven't eliminated the faults of these issues nor added avx512, the question is a matter of Use Case more so than just give me features alone. It would be nice to see AVX added and 32 pcie lanes on the 12 core AM4 Parts, because that's a lot of dough to spend on those parts. BTW Moore's law is nearly dead, and this is why they are focusing on Features, and additional Cores and other technologies are beefing up, such as PCIE 4 for example, or DDR 5 coming.
I think you mean "pressure sensitive film"? Our lab guys use it to measure contact of feet on the floor and contact patches inside cadaver knees and stuff like that. I know Fuji makes some, I think we also use a 3M variant. Search for that term and it should pop up something similar.
I can only find Fujifilm Prescale, and that's pretty stupid expensive, and sold in more industrial quantities. I haven't looked at places like alibaba yet though.
20:05 My 2 ¢ on this: I have observed it over the years, that developers simply do not care about optimization anymore. Like Steve said, the hardware can just brut force it, so why bother, eh? Back in the day, where the hardware was the limiting factor, there were all those nice tricks and 'somke and mirrors' used by devs, to get the look and the fluidity they needed for their game, on the hardware of the time. No it's not an issue as much, so ... why bother? They just don't. That's why many games now run horrid compared to how they look.
Similar with other Software, too. My current Discord instance consumes 260MiB of RAM. That would have been an unbelievable amount of resource waste, back in the IM/IRC days.
I have to disagree. Game studios keep pushing themselves and the hardware to new limits, both because of competition and out of sheer enthusiasm for the art of making games. See what Guerilla did with Horizon Zero Dawn. Or look at the developments regarding PBR and what that meant for texturing and lighting and for the art pipeline as a whole. And if it's not graphics, it's AI, not only for enemy tactics but also for procedural environments and animation. And don't forget the huge difference between the quality of games at the beginning of a console's lifetime and at the end: the hardware hasn't changed (much), but the developers have learned to harnas the system and squeeze every bit of performance out of it.
A question for Tin and Kingpin: What makes a good PBC for overclocking? Why are the EVGA Dark and Kingpin boards better for overclocking than "normal" PCBs? Additionally, how much of a difference does the PCB make compared to silicon lottery in performance, especially in terms of memory?
That's whats pretty brilliant about AMD's method of supporting a platform across so many generations. Once you are on the platform at any price point, providing a wide upgrade path will sell more chips. Between actually reasonable price reductions on older parts, and meaningful performance improvements between generations its kind of a win/win for them and the consumer. The 4790k is still stupid expensive for its age, and while I thought mine was dead (after being handed down to my kids) it turned out to be the asrock z97x motherboard (also what I felt was too expensive to replace). They got a B450 with my old R9 Fury and a 2200G and can get upgrades when I do.
I am a HUGE fan of SFF systems (building one currently), and I would LOVE to see you do content on it, but I fully understand your viewpoint in why you won't cover it. I'll still watch all your videos though!
"I don't ever want to grow to that size too" *crumples up resume* GN will never need a guy to stand around and occasionally look busy. Dad was right again :(
One restriction of L2$ is the fetch bubble. Modern branch predictors can memorize code paths that can't fit in L1$, but sit nicely in L2$. However if access to L2$ creates a fetch bubble too huge for the frontend to hide, the core would stall and the benefit of a huge branch predictor is lost.
Questions for manufacturers: how can the technology business be more insulated, mobile or modular, in order to withstand the problems that are occurring with the world wide outbreak of things like coronavirus. These are starting to come more often as our world wide integration increases across both technologies and social barriers.
20:55 They will go more real-tracing, easier from the dev perspective because no lighting issues in production because that effort slides to thew user (and their gpu), and that requires horsepower. Hopefully it will go like the shaders, in ye olden days there were seperate vertex shaders and whatever the other ones were called, then it became just shaders, graphics cores can later on become a tad more versatile and all cores will be raytracing capable, which will probably aid gpgpu use on the desktop. 25:45 Better question is why no L4 for apu's? Really fast L4 to bridge ram and the gpu.
And if VR will spread more we need in future gpus capable of 4-8k res + raytracing and 90+fps (depending on headset) all the time. For that we will need insane compute power increase.
Hearing what Logitech had to say about the G5 mouse makes me extra happy to have bought one a few months ago for 5 dollars. The thing just sits in my hand so naturally and feels like it's built like a tank
Question for the overclockers. Regarding extreme overclocking (using LN2 or whatever), what do you see the point of it being? Aside from getting the biggest scores on some benchmark, how do you see this as helping with normal day to day usage, if at all?
AskGn: Are manufacturers going to start making fabs/expanding factories from china to taiwan in the future? (Mostly applies to dram factories as they seem to have had a higher demand than other products)
Question for Taiwan: for mini-ITX builds, there is a thread on smallformfactor[.]net suggesting a new format, Flex-ITX. How hard is it to alter existing formats of a motherboard? I would provide a link, but external links get deleted on youtube. The thread goes into great detail and I would love some more info from a manufacturers perspective.
Questions for ExtremeOC'ers: When trying to go for crazy high OCs on GPUs do you perform PCB modification often? Like replace smds, caps, or add additional power stages or do you just stick to GPUs like Kingpins or Hall of Fame cards. Also, when you do modify the gpus what do you often try to fix? Power limits? Some weird stability issues? More Extreme OC limits? Lastly, what's the coolest or craziest mod you have done? Thank you.
I can chip in for CPU overclocking a moment. Most insane thing I've done with my old 4790k: I delided it and cooled it with a somewhat DIYed two stage refrigeration system. It held down the CPU to -70C under full load. Got some sweet scores from it. The second stage of the cooler ran on ethylene, without load you could go down to -100C :D This setup would also work for GPUs, it just would be freaking huge!
Thank you so much for your effort to eliminate those single use plastic bags! And also talking about it. Lets keep working on raising awareness, and get people to consider that seemingly small things can add up to huge differences in the long run. I look forward to a day that if an average consumer opens a product, that if ecologically irresponsible practices are used, that average consumer rethinks supporting those products/businesses. Once again, you made another great video, keep up the great work.
Question for kingpin or any other Overclcoker..........Is there a way to get AMD's PBO to boost higher? Perhaps in some wierd AMD CBS settings in the BIOS?
ColtaineCrows yeah I saw them,but even he says that PBO scalar does nothing and that you can't really get higher than the stock boost levels,which sucks....just wanna actually OC these ryzen chips,I may have to just build me a Roboclocker or something
Question for Experienced Overclocker: Is there a way around the inability to set max adaptive vcore voltage below spec in X299 BIOS? As an example, with my 9980XE I'm stable at 4.5GHz all core at 1.15v, but I have to set voltage control to Manual in order to achieve that voltage - with Adaptive or Offset voltage control, it's forced to about 1.23v regardless of what I set as max voltage. My motherboard is specifically the Asus ROG Rampage VI Extreme Omega.
Damn, would've liked to see you tackle SFF again. Not sure if you really like this solution to it, but this is what I'd like to see from SFF reviews: The best cooling possible. In SFF builds, your challenge isn't "how much hardware do I have to buy to make this hardware cooled" like in ATX builds. Even in the walmart case, if you put 3 rads in there, it'd probably be fine. But in a Dan Case, you can't do that. The limitation is the case. So I want to know before I buy: what's the most I can get away with putting in here? So a standardized set of hardware (at least cooling) doesn't work. Sometimes you need a 120 or 240 AIO. Sometimes you can't do that, and need a low profile downdraft cooler. Sometimes you can fit a long GPU, sometimes you can only go half length. Sometimes even a blower makes the most sense. I like to see the "best" config, and know "if I dump in the money for cooling, what can I fit in here"?
Question for Kingpin / Overclockers: What has been the hardest thing for motherboard manufacturers in the past, and going forward, when it comes to overclocking: physical components and layout/connections versus BIOS capabilities? And why?
Steven Gibson, Raytracing will be pushing graphics developmemt for the foreseeable future. The goal is for all lightning, shadows and reflections/refractions to be raytraced to achieve actual global illumination. Currently we only have limited raytraced lighting and even then we need de-noising, as we have too few rays.
Question: As a customer we see all these channels giving us a value per performance rating for components they test. That is why the 3600 is so highly rated. However, I find that there is a lack of a measurement that includes where you coming from. Like: How much extra performance do you gain from the system you are coming from. It would be really cool if some kind of archetype systems of older age could become part of the calculation. Couldn't we do something like: "Hey, if you come from an intel3570, buying a ryzen3600 would give you X amount of performance increase, and this offset between the two is then broken down in $ per performance increase. This would be a really cool sheet to check for when considering an upgrade. It basically would help you determine how much real performance gain per money you would gain for your upgrade.
@@Akkbar21 his chip does not seem to hit higher max clocks when using pbo, it just improves the average clock speed (he has a 3700x and a 3950x) my 3600 can get higher clock using pbo, but when i tried it i had stability issues, but the bios has had a lot of updates since and i have not tested it since
Bonus Ask GN(Steve) video for public viewing on the secondary channel -- this one answers a bunch of bike questions from our viewers: th-cam.com/video/Ntl2QlckFIM/w-d-xo.html
Get access to our bonus episodes and content on patreon.com/gamersnexus
@@Whatamood it's good.
Could you ask kp what it will take for evga to build out amd motherboards please
Not a question but I need to say it. I respect the hell out of what you do, Steve. I can't thank you and the team you've built up enough for your hard work. I've only been following your channel for a year but I've watched each and every one of the videos you publish and they are all dynamite man. I've learned a lot about the industry, hardware, the TH-cam world, YOU, the team, how to approach challenges in your life and work etc etc. I don't think you hear it enough, so from a huge fan: You guys all kick ass and I hope you're having an awesome time in Taiwan.
how long do u think its going to be before consumer overclocking is useless?
I do watch almost all of your videos
Question: Would you ever consider doing partnership with manufacturer to create a GN designed case in the same vein as der8auer did? I think community would love this. Then let der8auer do the review on it :-)
It's just a test bench with a mesh box you lower over it
I don't think any manufacturers out there is brave enough to try to build a case to their standards.
"This fretted gossamer spider-silk dust filter is great with an 88% open surface area but it's a little fragile. I was thinking you could probably chemical vapor deposit a three 10nm layers of corundum on it so that I can't poke a hole in it if I stab it with a screwdriver? That'd be great. I've also come up with this new claw-shaped weave pattern so that IF Snowflake decides to sharpen her claws on it it will legit sharpen them. Can you work that? GREAT!"
Massive ethical issues with future reviews maintaining the relationship though, unless it’s specifically a one-off thing
@@depth386 wouldn't that also be true for der8auer? And with Noctua+Linus Tech Tips?
i would buy it hard
Im here to support your content and your algorithm. Stay safe while traveling!
If i say human malware is it more supportive to the channel or i should write its full name? lol
@@schumbo8324 Hey fuck it, we all gotta eat and misewell try and make a living out of what you enjoy if you can, automation is the key to that.
I wouldn't be too worried about analytics at this point, the US still has friends 😅
(Question for Manufacturing): When will the consumer market expect to see high capacity SSD's (10TB +)?
I think that 8 TB will be the largest capacity most consumers could conceivably afford for the next 3 years or so.
They do, but they are price limited. They have much much shorter lifespan than spinning rust and aren't worth enterprise ssd size which typically will be the reason for larger sizes, not consumers
The industry is pushing cloud services why would they want you to have high capacity SSD's?
@@mbsnyderc because unless you have fiber gigabyte minimum, an ssd is faster (even with gigabyte a directly connected ssd is faster, with good ssd's being 2-4x the speed)
@@bradhaines3142 in an enterprise environment? Not even close. Closer to 3 years.
Where is the cost difference between aluminium and steel cases? How much difference is in the raw material? How much in tooling or other stages of manufacturing? Does the cost difference justify the massive retail price difference or is it mostly just "premium" marketing?
Aluminum is roughly 5x the cost of steel per pound (.35/per pound for steel vs 1.52/lb for aluminum) I don't think the tooling would be any less for a different type of metal.
the weight definitely effects shipping/ moving
Aluminum sourced in high quantity for this type of manufacture is usually more expensive by a factor of about 3, and is usually about 20% more expensive to assemble, though assembly costs may be close to parity if no welding is involved.
2 major issues, 1 tax on importing steel is much higher to U.S. and steel is quite a bit heavier, while not an issue for 1-2 cases, but when shipping a container with 1000+ cases, it does become an issue. Besides do you need cases that use steel? Do you find yourself deforming a lot of aluminum cases?
Its funny for a case i prefer steel 100% of the time. its more durable and i have seen many alu cases with screw holes being destroyed. i even filter on it as i refuse to buy or sell a alu case as in my opinion its a matter of when it will fail rather then if. latest case i bought the factory ruined the gpu screw hole and just ripped the threads like happens all the time. thats not happening with metal unless you try hard. same on my 1200 alo road bike the brake just ripped off die to a factory flaw in the mouse screw hole. its a failure waiting to happen. its a weak material.
30:10
Got to admire Linus for him willingly be able to take on such an empire and the risks and rewards for keeping 30+ employees constantly working and making ends meet.
The industry overall for content creation has been rough and uncertain and for Linus to go from a guy who filmed unboxings for a side channel for his employer to someone providing a living for 30+ employees is nuts. All the while literally being the face of the channel and subject to scrutiny and stress. Don’t blame him for wanting an exit path eventually.
Question for Overclocker(s): What do you think about nvidia GPU Boost 3.0 and similar auto OCs (Especially CPU auto OC) and do you believe manual overclocking will become more of a niche as these technologies become better?
Feel free to reformat my question. English is not my first language. Main point I'm trying to get to: Will we ever get good CPU auto overclocking?
Want to know as it was interesting to see SiliconLottery not carry AMD zen 2 CPUs.
@@BromTeque Your English is very good!
well as a general idea you will almost always be able to push manual overclocking that tiny bit more imo but it's practically already at the point where the difference is negligible
Linked to this: why does intel, while laggin behind in performance, still leaves more performance on the table than AMD? I find it similar with Nvidia GPU (before Vega) they overclock better than AMD cards. I rarely see RX480 / 580 getting more than 100mhz on memory while on Nvidia cards usually i see around 300mhz . All this from an AMD fan but system builder point of view.
@@gabrielecarbone8235 get a vega 56. See how much you can get out of one of those...
question for taiwan: how difficult is motherboard trace design and layout, and in general what is the process of designing them?
Didn't GN already answer that? th-cam.com/video/cnAFTMaS5R0/w-d-xo.html
It can get rather difficult. The PCBs for motherboards can get anywhere from 8 to 40 layers. The problem becomes making sure that when you do your routing you follow the documentation from the IC manufacturers. For example, gigabit ethernet controllers require at least four layers, and in some of those layers certain wires need to be paired together so there isn't any cross talk on those traces. RAM alone has like 258 odd lanes that need to feed into the cpu socket and be impedance matched.
The process for designing them starts with listing out all the functions you want your pcb to have and do. Then you start picking the integrated circuits that will allow you to achieve the desired functions. You check the documentation to make sure the ICs perform to the specifications you need. You make sure that they have the right communication protocols. For example, is it using I2C, SPI, etc... to communicate. You have to make sure everything can transmit data to what it needs to. Then you have to look at interference. For example, you may not want to put a switching voltage regulator net to a wifi IC as switching reg release a lot of EMI noise and this could really mess up your wifi signal strength. Once you have figured out the nitty gritty with com protocols, physicial limitations, you build a schematic and connect everything together. You add all the supporting filtering capacitors, decoupling capacitors, resistors needed for IC regulation/feedback loops. RAM especially needs a lot of decoupling caps because the memory IC's they use are so damn sensitive. Not to mention everything has a certain voltage that it is happy with, typically 1.8v ,3.3v ,5v ,12v. You need to route all the power traces from the PSU so that each chip receives it's necessary power. If the power supply doesn't have it, then you need to make a voltage divider that converts it to what you want with resistors. Then once your schematic is done you do an electrical design rule check. Depending on your PCB software (Altium, Eagle, Mentor, KiCAD, etc..) you are able to test for shorts (faults) you are able to make sure your inputs go into outputs and vice verse, you make sure that you have no stray wires that aren't connected. Then once you do that you make sure you have your footprint library up to date of all the ICs that you use. All of them have different package sizes and when the PCB is milled out then acid washed it needs to put the pads for the ICs in the right places with the right tolerances. Once you have all your footprints you start laying out the pcb placing the components in different areas based on the design. You know that there is going to be a lot of IO near the back pannel, so you know you are going to want to put your various connectors there. You once you have everything placed. You generally on intricate boards will make one side a power plane and one side a ground plane. Then you need to make sure that the ground plane is either clean or dirty depending on whether you have really noisy signals grounding to it. then as we go into the core of a PCB, typically FR4 we route all of the traces which are represented on the schematic. Then once done you do another design rule check but this time for the physical board. Once done you export the gerber files which are files that tell the fab shop where the traces, vias and various pads are on the board so it can machine it or acid-wash it. Typically everything these days they choose ENiG gold coating because it doesn't corrode like lead or tin will over time. Typically when you send it to get the board fab'd you do what is called turn key. So the fab house not only makes the pcb, they also create a solder stencil for solder paste, and use a pick n place machine to build the board, then run it through an oven to solder everything at once that doesn't have plastic.
And that's how it's typically how it's done, mileage will vary on depending on what company you work for.
@@christopherjohnson4362 fantastic answer. I figured with the massive numbers of traces involved there'd be more automation on laying out traces for basic ICs and such, then people would go back over it again to make sure there wouldn't be too much interference, but I suppose the way you described it makes more sense. Thanks!
Some of what he mentions is more related to hobby level boards. And he forgot some things like breaking out BGAs. Modern ICs have connections all along the bottom surface rather than just the edge. These internal pads have to be routed out. The more of them there are, the more difficult it is. Prime example being the CPU socket. That alone is a significant factor in the number of layers you're going to use. I have never designed anything that complex, but I would probably start by placing the important components and features. Whether it's for mechanical, thermal or electrical reasons. Some will have a fixed position (like mounting holes or PCIe slots where it's prescribed by standard), some will be more flexible but you have a general idea (like socket, DIMM slots, rear IO or internal SATA connectors). Then I would break out at least the socket. Sooner or later, you'll have to breakout everything so you might just as well. Then I would route the high speed traces like PCIe and RAM. Those are difficult. There are plenty of rules and best practices you need to keep in mind. That's why you do them first when you have a clean slate. Then I would probably look into power supply for power hungry chips. You already did some of that as part of the breakout as you want to put decoupling capacitors as close as possible. That's why they're often found right on the other side of the board. On a complex, multi-layer board, you might end up with multiple ground and power planes. First layer typically has high speed traces on it (there might be a ground plane beneath it). If you're interested, you can find guidelines online for laying high speed traces. You'll learn about impedance matching, guard traces, layup. I don't know about using voltage dividers to supply voltages which are not available from the PS; generally, you typically use local voltage regulators. Then you can start on the lower speed stuff. If there is any analog circuitry, it definitely needs a priority (mixing analog with digital requires forethought). Generally speaking, autorouters don't do a very good job. I can't speak for the top end packages which are eye-wateringly expensive (you really have to do it for living). On the other hand, there can be a load of trivial traces. I wouldn't expect a motherboard designer to hand route everything, not at all. And you can use them selectively. So you could try autorouting the high speed lanes first. The expensive packages have tools that simplify things like length matching for RAM. They also have tools for things like signal integrity. So you can look for potential problems even before making a prototype. Generally, you proceed from the critical and difficult to the mundane.
Everything is relative. If you do it for a living, it's routine. Currently, the PCIe 4.0 might be a bit of a headache because it's fairly new. But they'll figure it out. If you're a hobbyist, it's practically impossibly difficult. You don't have the experience, the software that would make it easier is very expensive and the hardware to test your work is very expensive as well. Perhaps a better question would be how many man-hours it takes an experienced designer to design/ layout a board with something like X570. And of course, you can ask specifically about the tools they use - like how much they rely on autorouting.
A question for GN: Do you, Steve, answer the "Ask GN" questions by yourself, or do you sit down with the team to make sure you have the whole team's opinion on the question?
Ask the experts: Why TF can't we get standard front panel connectors or a standard pinout for the PSU side of modular cables?
@@hotaru25189 Iows, pride and probably because everyone must try to get everyone else to license and use their ( probably proprietary ) setup.
So pride and greed, classics.
"I think we can do better."
I mean really, why can't they just pin out modular cables like pass-through extension cables? Nobody needs to use anyone else's format. They are just complying with the connector specs for the different sockets on the board.
It's because PSU vendors want to ensure that you buy *thier* cables and nobody else's... the Minifit JR connector type is basically a defacto standard and if anything they are only making minor modifications so that it doesn't match other vendors. In short there is no technical or engineering reason why they can't they just don't because money and or liability if you use another vendor's cables.
@@Wingnut353 "Liability" ha! They may use that as an excuse for why they do it, but it isn't for liability. Cable extensions, adapters, sleeving your own cables...once the angry pixies leave the metal box, all bets are off. Besides which, you could easily argue that not standardizing the pin layout on those cables *and* removing the color coding on the wires makes the product less safe.
I love your work ethic, Steve. You keep yourself to the highest standard. Few people do this. Keep it up. Have been really enjoying this channel.
(Question for Manufacturing): Do you use recycled materials ? and if so what's the percentage of recycled vs newly produced materials ?
On the question towards the end.... 30min mark, very interesting and similar boat with our business!
It's hard juggling, maintaining and running a small business!!
Congrats!!!
@kingpin what's the weirdest piece of tech you ever overclocked?
I hope GN asks him this question!
BTW I've overclocked an iMac G3 by resoldering a resistor that controls the CPU multiplier (350 to 400MHz), and the ATI GPU could also be overclocked, though that was simply done via software.
*overclocks microcontroller embedded in....* you finish the sentence :D alot of micros are super easy to OC by as much as 25% too... since they are often designed with really good safety margins. Actually MCU overclocking competitions would be really fun and cheap to get into... kind of like the pinewood derby of OCing. Rules could be something like no heatsinks, no non standard copper boards 1oz copper only, any oscilator you like, any passive components you like and a specific MCU.
Re: L2/L3: When reading data the CPUs have to first check with every other CPUs if they have a modified copy of the data in their cache and grab ownership of that cache line. Especially with the awesome number of cores we're getting today things are getting very complicated tuning for all the different workloads: games, browsing, photoshop, 3D rendering/video edit/encoding, AI learning, etc.
The L2 size is a compromise in part for the circuitry cost & timing cost of L1/L2 caches checking/answering "No, I don't have your data, leave me alone." Larger cache means more to check and more to exchange out.
Having a smaller L2 causes the data to end up back in L3 sooner which counter-intuitively a smaller L2 can increase performance in multi-threaded workloads because by the time another CPU wants that data there's a better chance it's already in the global/shared L3 rather than still in the inaccessible (quickly) other-CPU's local L2.
A CPU can access it's L2 faster than it's L3, but *ALL THE OTHER CPUs* can access the L3 faster than a different CPU's L2 or L1. Multi-core changes the sweet-spot for cache sizes and single-threaded/single-CPU workloads aren't penalised too much by hitting the L3, when no other CPU is working it has the huge L3 all to itself but still can't use other CPU's L2 which is then a lot of wasted silicon.
depend on how many ways on l2-l3 cache ways and its function example victim cache on l3 ... way better than flash ur pipe line and wait few clock retrieving data from ram... so its depen on uarch and how good its branch prediction
@Science! This still holds true on single chip designs, But its quite a similar problem to NUMA. Adding to @Stephane you also have a Problemn with associativity and not just the MESI Protocol. To properly use a cache you would like to know which bits and bytes are the oldest and use a LRU strategy. Which gets increasingly complex with an increase in associativity, tho an increase in associativity often leads to better Performance in most applications. So 512Kb L2 cache is considered the sweet spot for performance in most applications (depending on architecture of course).
@ufster81
That's actually how Bulldozer was designed to work more or less. The modules shared FPUs and L3, the idea being that they would take turns and share the workload. The APUs sacrificed the L3 cache for GPU cores.
Bulldozer's main problem was that most software wasn't optimized for that sort of workflow, which lead to a lot of congestion, especially in FPU heavy tasks like gaming.
The CELL works in a similar manner, just with more complexity in how it can delegate tasks. It could even handle GPU functions.
@Science! Single chip Intels have the same challenges: The L2 is still per-core, while the L3 is shared. So a single-core/single-thread workload can only fill it's own L2 (and the L3). In that workload on a 4-core that causes 3/4 of the L2 caches to be unused, on a 18-cores i9 that means 94% of the L2 caches goes unused for single-core tasks. Putting more silicon area into L3 than L2s means less wasted silicon space.
And a multi-thread, multi-core workloads still wants more shared L3 so all the CPUs can share and pass the data around more efficiently without hitting RAM's comparatively enormous latency.
Is there any prospect for x86 designers to make assymetric core designs, like ARM SoCs?
Eg. Having a (few) single thread focussed cores with bigger caches and better IPC, with clusters of multithread cores centered around the L3?
I don't know a lot about Arm's μarch, so I imagine accessing the cache is different but I'm finna believe
So, I keep hearing about TSMC, but a while ago I remember reading about an agreement between AMD and Global Foundry. Where has GF gone now that all this new architectures are produced using TSMC nodes?
Good question for next time!
Global Foundries still makes the IO Dies for Zen chips because theyre 12nm instead of 7nm. Global foundries killed their own 7nm R&D and manufacturing when they did a large restructuring in the company, during this they lost AMD, so therefore I dont think they make 7nm chips, specifically focusing on 12 and 14nm in emerging markets
IIRC GloFo wanted to go for mass market rather than bleeding edge, even though they sued TSMC over 7nm technology for some reason. I do believe that AMD still has a wafer agreement with GloFo, and they're fulfilling that agreement through the manufacturing of the IO dies. I noticed that the 7nm Ryzen parts have two locations specified for where it was diffused, and I believe the Malaysian plant is GloFo and Taiwan obviously being TSMC.
This is all from my dodgy memory, and I cba to re-look it up atm.
TSMC.
AMD spent a lot of money I believe 2 years ago to get out of the contract with GloFo. Now GloFo still makes almost everything for AMD except for the 7nm stuff.
I think AMD still has to buy enough chips from GloFo to not be in violation of the agreement, but now AMD can use other Fabs as well and no longer limited to GloFo.
But then again this is likely the reason why AMD is still making Polaris cards and rereleasing Zen processors like 1600af
GloFlo has a dirt cheap 12nm processes they use to pump out cheap 1600 af's 2700x's and they use it for all the I/O dies
The single use bags are great to hear about. It's crazy to see so many bigger companies just ignore the impact of their waste. You guys go out of your way to ensure good practice in every project I see. Thanks GN team
In regards to L2 cache sizes.
L2 is typically around 128-512 KB per core.
This might not seem gigantic compared to the handful of MB or more of L3 that most CPUs have on offer, but L3 serves a fairly different role compared to L2 and L1.
Now the role of cache in a CPU is typically quoted as being used for "reducing latency", why this isn't correct we will get into.
Latency is honestly not a big problem for a CPU, we can generally fix the problem of latency by simply decoding instructions earlier, and putting them into a queue. This gives us the option to prefetch data many cycles before it is going to be executed. This though means that we also need to prefetch both sides of a branch in our program, effectively doubling our bandwidth requirement from that point on, and any additional branches down the line will just as well increase our bandwidth requirements. (This is part of the branching problem, and branch prediction can partly fix this issue too, but in case of a miss predict a lot of architecture implementations still prefetch at least the first branch regardless.)
This can very quickly lead to rather exorbitant bandwidth requirements. So the frankly pathetic bandwidth over to main memory will not be sufficient (yes, DDR4 with its 20+ GB/s is rather lackluster as far as even a single core is concerned). This is why we add cache.
With caching we don't need to fetch data from main memory, but can instead fetch it from cache if it is in the cache.
This though obviously introduces a new problem. How many cycles does it take to check if the data is in cache?
Well, the answer is, it depends on how much cache you have.
L1 for an example is very small, and therefor generally fairly easy to check all its content. Now L1 is typically extremely parallel in how it searches for cached content, typically able to handle 10+ of cache look-ups every cycle, meaning that it is extremely fast, but also extremely expensive. (64KB of SRAM needs about 2 million transistors, L1 in most CPUs can have over twice that amount of transistors...)
L2, is substantially larger, and generally won't get talked to as often, after all, L2 is only contacted if L1 has a cache miss (and that is typically less than 5% of all cache look-ups that L1 handles.). (in some architectures L2 is sometimes called on regardless, for cache coherence reasons....)
L2 isn't as busy as L1, despite typically having 2-4 cores poking it, and we have lots of time, we can instead focus on making it more cost effective instead of being able to respond instantly.
L3 is the least busy cache level, though since you typically have many cores in a CPU, L3 tends to be more busy then L2 in some CPUs. But When you reach L3, your core is most likely stalling when you finally get the data... And if you have a cache miss, you better hope that the kernel switches thread, since now you are going to main RAM over a comparably slow, high latency connection.... (Just to paint a picture of how slow it is, access latency for DDR4 is around 5-15ns. Or from a 3.8GHz CPU core's perspective, 19-57 cycles, or around 95-750 instructions. (Thankfully DDR4 will read you back some 64 bits of data in that time, while a well designed L1 could have provided those 750 instructions with typically around 64 bits of data each without much hassle. Ie well over 100x the bandwidth of DDR4. Not to mention that the memory bus might be preoccupied, so your call has to wait in line for a "few" more cycles...))
Making L2 larger would risk stalling each time we fetch data from L2. This isn't ideal, since we would be wasting time.
Making L3 larger on the other hand is a very different story. L3 serves the purpose of making sure that we don't instantly bottleneck on the frankly pathetic bandwidth that the main memory buses have on offer. That L3 gets a bit slow is less important, the only constraint here is how fancy our caching system is, and how much resources we wish to spend on SRAM.
So why not prefetch even earlier? Surely that would fix the stalling issue?
Well, it fixes stalling, but now you risk having more branches, and thereby higher bandwidth requirements, and thereby making L1 more expensive.
Since each new branch means that we need to decode an additional instruction during the same cycle. And together with out of order execution that already pushes us to decode 10+ instructions per cycle just to keep up with execution.
Each additional branch would effectively require us to prefetch another 10+ instructions per cycle, so we don't want to risk decoding too many branches, since then we have a ton of instructions to handle. Each instruction having 2 or more variables, thankfully, a lot of these variables will not even result in L1 cache look-ups, since it will just use various registers instead. But it isn't unfair to state that 1 out of 5 instruction calls results in a cache look-up. (this though varies greatly depending on the code being executed. One can have no cache look-ups in 500+ cycles, or have them every cycle. So it can vary a lot.)
In The End:
L2 size is practically dictated by how many cycles ahead of execution one can prefetch, and how large of an array one can effectively index and fetch from inside that amount of time.
And how many cycles that is, is typically determined by how many instructions one can expect per cycle, + any additional overhead due to branches.
And that in turn is dictated by how many cache look-ups L1 can handle per cycle. (And how good one's instruction decoder is)
In short, larger and more parallel L1 and faster decoder = possibility for larger L2. (But this comes at a cost, and a lot of applications wouldn't noticeably benefit from it.)
Increasing L3 cache tends to have more noticeable gains, since most stuff that is too large for L2 tends to instead be bottle necked by main RAM. Though one needs a lot of L3 to make a major change here. But if the dataset of an application is small enough to fit in L3, then the application can have little to no need going out to main RAM. (Though, L3 only partly supplements main memory bandwidth, but it doesn't increase actual memory bandwidth. To increase actual bandwidth, we need more memory channels.)
Also, I should point out that I am greatly oversimplifying things here, this is a youtube comment, not an in depth article on system considerations regarding L2 sizing.
Wish I could save TH-cam comments, thanks for the (relatively) lengthy write-up!
@@Leap623 No problem, always nice to see that people find my walls of text as informative.
Although, I could likely cut out a few sentences here and there and condense it all down a bit.
At least I didn't waffle away on the topic of how all this gets far more maddening with cache coherence checking between NUMA nodes... And the various methods of partly resolving such issues.
@@todayonthebench Would there then be the possibility of an L4 caching system that could supplement L3 caching, thus reducing demand for main memory being demanded by the system?
@@XRioteerXBoyX First of, main memory doesn't get damaged from just using it.
The problem is that main memory buses tends to be extremely slow compared to what a bunch of cores actually need. So we just get the computer equivalent of traffic congestion.
In regards to L4, some systems do use it.
L4 is though a rare sight since it doesn't really make much sense.
First off, L4 would need to be bigger than the already huge L3 for it to be effective, making it rather expensive. Unless one uses DRAM for it. (This works since we are trying to solve bandwidth, not latency.)
The next problem is that it needs somewhere to be. Preferably on the CPU chip carrier as to not occupy pins on the socket. (though one can make it a "complicated" memory controller out on the motherboard. That then in turn talks to main memory.)
Though, L4 has the next bigger problem. And that is, L3 can already be arbitrarily huge, L3 can already use tens of GBs of HBM memory if one so desires, since when we reach L3, the core should be at the verge of stalling regardless.
So as long as L3 cache indexing and fetching the contents from its memory is offering more bandwidth than the main memory buses, and preferably has lower latency than traveling through the memory controller queue, out to main memory, and fetching the contents there, and getting back again. Then L3 has no actual limits to how large it can be, rendering L4 rather pointless.
In the end, it has proven cheaper and more effective to just fix the actual bottleneck, ie give the processor more memory buses.
As an example, all CPUs used to only have 1 memory channel.
These days, a low end CPU has 2.(LGA1155-LGA1151, AM4, AM3, etc all uses 2 channels)
Higher performance system usually have 4. (LGA2011, LGA2066, Threadripper)
In the server space, LGA3647 has 6 channels, Epyc has 8, and Intel Scalable has 12.
"Do one thing really, really well." - Steam Whistle brewing. :) You are kind of in a unique position among tech content creators - you balance being an effective media outlet with being more technical than most other popular channels without being super-technical. I think that's your sweet spot. I watch your channel to learn. I also appreciate your environmental responsibility. Oh, and your seeming disdain for companies that just puke RGB on products. :)
Question for overclockers: I've heard that increasing (GPU) memory frequency can decrease performance because the memory ends up having to correct more errors. How does this process work at a more in-depth level? How does the hardware know there's an error, and how does it know how to correct it? Are there any ways to log these corrections in software?
very interesting because on Polaris there is an actual error counter but on some tests like firestrike i can see no artifacts but i see mem errors show up in hwinfo, while in TimeSpy i see light spots in green and white but no memory errors show up!
Increasing GPU memory frequency or system memory frequency?
You know there are errors when artefacts starts showing on ur screen, which you can count with your eyes. If you mean DRAM then run a stress test with MemTest86
Are you talking about ecc memory? This is the only type that will correct errors, by including a 9th bit they correct based on whether a bit flips or not, as a very basic explanation. Standard ddr4, overclocked or not will not error correct.
I actually had that happen today - I boosted my GPU memory frequency 300mhz and the Cinebench scores dropped from 4826 to 4746 - ran test multiple times... CPU is 3700X with the 2060 KO Ultra GPU and 32GB 3600 DDR4 RAM
Logitech: "Our G5 was too good, and didn't break enough to the point where our sales suffered"
Me, a G500 owner: *nervous sweating*
*laughs in M510*
I have a G5 laser mouse that is 14 years old and still works great. I finally upgraded last year when I built my new machine back in July. I'm now using a G-Pro Wireless.
Meanwhile I've found that they added planned obsolescence in the G403. The scroll wheel is built such that after enough middle-clicking, the scroll wheel will break. That's because the part of the axle that's responsible for actuating the scrolling itself, is very thin and molded onto the rest of the scroll wheel very awkwardly.
I have a G500 and G500s (bought the S because the left click button started to wear out after about 10 years where it either double-clicks, or doesn't click instead of working properly). Neither are in daily use anymore but they're still one of the most comfortable mouse size/shape designs I've ever used.
I had G5 for 1 to 2 years it was a great mouse but died. Then moved on to MX518 and the same thing happen. Guess what now I am no longer a Logitech customer.
Question for kingpin (and other overclockers): What do you know that the engineers don’t? Is it really just “golden samples” plus liquid nitrogen?
yes, they work with engineers and are.
question for overclockers: cpu deterioration is caused by voltage or heat subsequent by higher voltage?
if it’s heat, can the deterioration be stop with exotic coolers?
"Call it lazyness if you want" I do want, and I do call it lazyness. Optimisation is the hidden art of software development that is slowly being lost to time
Fortunately consoles will never let it die out. There is no opportunity for devs to fuck off on optimization for a static piece of hardware that wont change for ~5 years.
@@oscarbanana6159 where have you been? Games are reaching the 20gig range for consoles, and broken as hell on release. Optimization and compression have not been a priority for years on consoles.
@@calebb7012 Storage is cheap compared to processing power. Compression use less storage, bug take more processing power to uncompress in real time. To me, they can go as big as they want as long as it run smooth.
@@oscarbanana6159 hehe... reminds me of shadow of colossus running at 12fps on playstation 2 and metal slug slowing down oh intense scenes on ps1.
Been following you for years now. This video, after the last 3 topics you and your team gained so much more respect from me. Keep up the mood and the great content!
Safe travels to the GN team! I hope there's no hassle and delays on your way back due to the panic of the new virus
It's been great. No issues at all so far!
I rarely comment on this channel videos..
Cause it's already super high quality.. but
I really really appreciate the clear answer on 30:10 , his short answer is Quality Over Quantity + extra busy hours
Rarely you see people prefer extra work to maintain the highest quality they can achieve, I like people who're loyal to their work
I am looking forward to your factory tours. I enjoy the "How It's Made" GN Edition!
Safe journey to all the GN crew. o7
I'd like to see a HowToBasic GN segment. :P
Factory tours are nice watching coming from 40y machinist who sees mobs of suits clueless walking the main aisles quit often
At 28:56 is why I love and respect GN. Quality is in short supply. And yes, automate the hell out of everything. This is a big part of what i try to do.
Hand this guy a medal for always being so proffesional!
The set is slowly but surely turning into a weeb cave.
Weebs Nexus
What’s a weeb?
@@radicalxedward8047 It's stupid internet slang, what else do you expect these days?
RadicalxEdward a person who obsesses over Japan, particularly anime.
Anthony F.
Like an otaku? As you can tell by every platform that’s ever had a “RadicalxEdward” all being me (and many of the ‘Radical Edward’ and ‘RadicalEdward’ ones too) I’ve been big into anime and japan since I was a little kid, been all over 4chan, tor, the onion, Reddit, social media, etc and have never in my life come across the term “weeb”
I'm super surprised at GN's environmental concern (over multiple videos) and I gotta say it's so good to see that you guys give a damn. And I feel like it's not just fake greenwashing. As you said, the single use plastic bags could have stayed the same and nobody else would have mentioned it.
Feels like I’ve been waiting for a new AskGN forever!
Time stamps in your own video. Pure genius very nice touch man
Steve, love your sedated ethical approach, retooling to remove single use plastic is 100% commendable, as is the fact you have not jump on the ' look how environmentally friendly we are' bandwagon like some others out there. 🌳🌍🌲
Best Buy employees don't know much about anything. During my interview there for the computer department, I had to explain the certification scale of PSU's. And also what a PSU is. And note that these were the department supervisors. This happened at 2 stores. Lol. Then they told me I'm not a good fit.
@Buffy Foster yeah, what they do there is very minimalistic.
you knew too much. Occasionally for a laugh I'll ask their computer area people questions just to see what comes out; it seems like their training is primarily covering popular brand names, which aisle various parts are on, and trying to sell extended warranty services. They've always been friendly to me, but I knew more about PC building and troubleshooting as a kid in the Windows 95 era (heavily due to breaking the family PCs so many times) than these poor Best Buy / Geek Squad kids are taught.
@@kalmtraveler Exactly. You don't want someone who knows too much, because then they're going to tell someone when they're buying more then they need.
They had a great roll model going with price match and having the new Ryzen cpu's on the shelves as to evolve into a Micro Center type store .. because there stores are located close to all major collages in my area but just to dumb to see it and move on it as to scale back the laptop overkill area and open up custom build like the old (Comp USA) early days .
I know of one Best Buy where the IT manager is a former black hat with 160 IQ and a MS in programming...
I think it's more likely that they either thought you were slumming for a temp job and they wanted someone long term...or maybe that during your lecture on PSUs, they decided that you'd confuse customers and rub them the wrong way with your holier-than-thou attitude.
I was thinking maybe the 1600AF exist as a another way to fulfill the wafer supply agreement at Global Foundry. Because they get the I/O dies from them too for Ryzen 3000.
@Paul Robertson , what are you talking about. GF does 12nm known as 12LP, feel free to look it up.
@@420247paul 12nm is an optimized 14nm from Global Foundries. Backup Plan has it correct.
That bromance .... even K-drama can't compete!!!!! xD
There are primarily three ways to increase GPU load:
1. Improved physics, this is mostly CPU, but technically, ray tracing is part of physics (of light). So some aspects obviously can be handled by GPU
2. Improved assets, simply put, more polygon to handle.
3. Decreased optimization.
The first two cost money, the last saves money. So even if the cost of developing a game holds the same (i.e. not cutting corner in terms of decreasing cost), there is a path to quite a lot of increase in hardware demand on highest settings, until they cut optimization completely and spend all that money into assets. Beyond that, it would start to cost more money to make a more demanding game, not less.
At the same time, the software for constructing/generating the assets are also improving overtime. So the same quality asset will cost less and less to make, in other words, for the same money, you will get better and better assets. So in a way, it will also be an arms race between hardware development and those asset creation tools.
Thank you for trying to answer my question. I'll be very interested to see what the reason is in a future update!
L2 cache input:
In a course at university we were told that for all cache (at least in die) there is a tradeoff between latency and capacity. This relates to the fact that the larger capacity increases physical size, meaning data has to travel further, (dis)charge more capacity and potentially go through more circuit which takes longer (and consume more energy).
To mitigate the impact of a low capacity while retaining low latency more levels are added as you would need to fetch this data more rarely (which is why it is located in the higher levels of cache) i.e. has less overall impact while still being significantly better than RAM (which can be seen as cache for your main storage).
29:58 "If I can't do it really well [...] then I don't do it."
Thanks for addressing my question. I'm still disappointed I couldn't prod GN into doing something with SFF again, but your small team is working on many things so there's a lot on their plate already.
I saw your list of pitfalls for CPU cooler testing and for your own sanity I don't recommend being that rigorous with absolutely everything. I mean, you didn't test thermals for the Cute Pet case since that was more focused on the novelty and build quality. Perhaps I just need to find an SFF case under 20 liters shaped like a cat or with a waifu printed on the side and boom, we got some SFF content again!
Joking aside, Steve laid it all out clearly and even said "Sorry" at one point so although I really want SFF content I can't really be mad about it.
REALLY looking forward to new factory tours. Love that stuff. Reminds me of watching Mr. Rogers as a kid when they would show stuff like that.
26:28
I do have an issue with single use plastic bags, but if they’re resealable plastic ziplocks of a unique set of dimensions I tend to keep them , especially if they hold parts for organization.
The Dallas MicroCenter lowered the price of the 3900X to $400! Amazing performance at that price point!
Goddamn that's a flipping steal!
I wish I had a micro center that wasn't 4 states away.
But really unless you know why you need it you just don't. No gaming doesn't count. A 3600X and especially a 3700x and a 9700K has more than enough cores for gaming and office work.I laugh at those with a 9900K even though I own one (I do hyper-v virtualization with 8 virtual machines with Intel RST raid on 4 ssds is my use case when not gaming)
Thank you #GamersNexus Thank you Steve and Crew for all the hard work you do to bring us these excellent and informative videos!
Thank you Steve for not going super big.
We all know what happened to small-medium youtubers when they decided to go super big.. not gonna call names but.. let's just say in most cases their content quality dropped significantly due to them trying to approach a more wide audience.
Laziness isn't wanting to stay at a small-enthusiast level, laziness is only reading specs and getting easy views likes most HW channels out there that do 1/10th of the work you do ;)
A good guy. Excellent content and a good crew. Steve and Wendell over at level1 are at the top of their respective games and who's word/opinion you can trust.
The bars that fill up based on his time and topic has to be one of the greatest, simplest ideas ever.
Question 1: Is overclocking worth it for normal day to day usage?
Question 2: Why is the left side numpad on keyboards (EDIT) not more common? There is a demand for it.
1. No.
2. Not enough demand to warrant it being more common.
1. No, but undervolting is the new overclocking, and is definitely worth it. Same difference.
2. ...uh. What?
Regarding graphics performance: Increasing resolution and framerate is not some artificial inflation of hardware requirements, it's a very visible improvement in image quality and the experience as a whole. It's just as important as (for example) getting better textures ingame. Speaking of textures: Scanning real objects is a thing and plenty of companies are working on implementing it in broad scale. It'll look awesome, but you can expect hardware requirements to match.
Can you overclock the chipset of a motherboard? and is it worth it if so?
Depends on chipset, but bclk overclocking will overclock everything, including chipset, often causing instability. Old chipsets you could oc, but would need active cooling
There is the BCLK thing which is typically 100Mhz and that’s how you get your multiplier for CPU where 50 is 5000Mhz. It’s possible to manipulate that 100Mhz base value but it has very little headroom and can brick things if you push it so I would basically tell you don’t bother.
Here from LTT channel love the content dude.
AU Optronics is in Taiwan. Would like to know if it is them keeping monitor prices high via panel cost or manufacturers. TV's are catching up and monitor prices don't seem to be decreasing as fast.
L3 Cache growth vs stagnant L2 size. Another angle, because some operating systems (Windows) lack core per thread consistency, threads tend to bounce around cores. placing the data in cache not attached to the core the OS moved the thread too. with larger L3, that increases the chance the data is still in a cache level accessible by the thread as it's bounced around the CPU like musical chairs, instead of an L2 or L1 that has access limits from cores it's not attached to.
Steve's point on latency vs size is the other angle, and a very solid one.
On that last Q, I bet y'all could get that Beve Sturk guy. He seems knowledgeable. I don't have any Qs, but keep up the solid content and have safe travels!
Unfunk: If you read this.
The reason for the L2 vs L2 discrepancy is that most caches are what they call cache inclusive. What this means is that if you have something in L1 cache it is also in L2 and also in L3. If you do some mental gymnastics you can quickly figure out that if you had a 1mb L1 with a 1mb L2 and a 1 mb L3 that you would have 1mb of usable cache. The best arrangement is to have the last level cache be the biggest and the L1/L2 be as small as possible. The next thing is that as that size of a cache increases so does the latency. So you don't wont your L2 to be so small as to put everything into the higher latency L3 cache. That balance has lead to 512k being the go to for quite a while.
AMD up until Ryzen used a cache exclusive design meaning data was not replicated this allowed AMD to have 512kb cache with the first Athlon 64's.
For some reason I hate the hole "doesn't overclock as well" thing. IMO that should be a good thing that the company knows what chips they have and how to bin and market them. If a chip overclocks well that would mean they have a chip that is good but they need to make artificial market separation or, they haven't put the RND into understanding the chips they have made so they just stick them in whatever box fits close enough.
That might even be a good ish question for chip manufacturers if you talk to any of them. How do they go about binning and sorting chips? We seem to be stuck in the i3, i5, i7 sorta thing for ages now. eg. low, medium, high... Office, peasant, GAM3R!...
I disagree that "doesn't overclock well" isn't bad. It's a good benchmark to understand the quality of silicon you just bought. Heavy binning hurts the consumer because it's the manufacturer nickel and diming you for maximum profit margin SKUs. Not even hitting claimed speeds under overclock cooling and voltage straight up tells you the silicon left behind from binning is low quality, let alone adequate for it's spec. If you can't even get good 3900s to reviewers that tells you how hard TR is eating up all the good silicon.
I would far rather have a 9900k from before they started binning away the best silicon to the KS. AMD's entire stack is binned, they already said so. While they still perform well to cost, you get the feeling you're using leftovers for the middle of the stack and the whole reason 3950 and up perform so amazingly but are rare. They have a lot of high tier SKUs to fill so you effectively have zero chance to get a golden sample without paying for it.
With the likes of the KS and AMD upper stack, it's no longer "you get what you pay for" it's now "you're gonna pay for what you get". AKA silicon lottery doesn't exist anymore. You're guaranteed to lose.
Man that talk at 23:28 Is some real damn Tawk. Everything is made to break/breakdown after a certain amount of given time.
I have a fan from the 50's that's been in the family for so long.
Still going as purchased,mean while some new ones have had trouble/replaced.
Question: Most cases I've used/seen have very little space behind the motherboard for cable management. A SATA power connector jammed back there seems like it'll snap off for example which, depending on where your drive mount is and how long the power cable is sometimes needs to be set back there. PSU shrouds have made this a bit better but:
Why don't case manufacturers expand the width of cases a bit to give some more room for cable management? I'd love to see 1/2" to and 1" of extra space but any extra space would help.
I'd rather see content once a week or more than you sacrafice the quality. love what you do and cant wait for the next vid. whenever it comes
Questions for tsmc.1. As we see more ARM based products including Ampere Altra at 80 core and Apple developing their based laptop/ipad cpus how long do you see x86 architecture continuing into the future? 2. How does tsmc plan to resolve quantum effects in future products below 5nm?
26:28 Next time you design tools get in contact with AvE (a youtuber) he knows almost too much about tools/tooling
his channel has lost a little life?
A question about PCBs and chips : How does the clock you set via software or bios translate to the "physical" clock? How does it get generated on the GPU/CPU physically (like the multipliers and alike)?
23:15 I just paused the video here so I can admire the expression. bravo
Question:
What the cost difference for a psu manufacturer is to manufacture an atx psu vs an sfx/flex atx psu at the same wattage and efficiency?
Question for Manufacturing: Is there any likelihood of seeing 3.5" format SSD's in order to immensely increase storage capabilities; particularly for the enterprise segment?
When you said maybe "hosting", it resonated with me. I miss the days of building boxes & playing with SQL.
GAMERS NEXUS: My question for engineers is why haven't we seen actual, real improvements of the hardware for CPU's? Now I know this sounds absurd, however, I've been able to get 5.3ghz since the days of x58 at about 1.478v, in fact, I'm still using it at 4.6ghz 12 years later at 1.372v. As a result, my 12 year old comp has better single core performance than the ryzen 2700x, and since most things still dont fully utilize more cores in the gaming world, 6 cores at 4.6 vs 8 at 4.2 ends up being almost identical as well--literally the only thing holding back the performance is pcie2 vs 3/4, so its a physical bottleneck not allowing me to use anything higher than essentially a 1660S in it vs my 2080ti (which even then, doesn't fully saturate pcie3). So its basically that and what... Shadows of the Tomb Raider and Assassins Creed are where, 12 years later, it actually matters?
For perspective: GPU'S in the same time have gone from roughly 8800gtx to the 2080ti. Why has there been such a stagnation on the actual performance CPU side when the GPU performance uptick has been incredible? Why are they focusing on smaller and smaller and more expensive to fabricate architecture vs say... 10ghz? If not 10ghz and more cores, why hasn't multicore been properly supported/leveraged when the technology is basically as old as I am at this point?
I'd be much more interested in 10ghz or core counts beyond 1-6 being leveraged properly than going from 32nm to 7nm and getting essentially the same performance, except, perhaps, per watt (60-90w 3700x vs 80-130w 12 yo Xeon [18 vs 22 cents p/10hrs]).
The simple answer is that the chemistry of what constitutes a transistor has not changed. The energy level to move electrons to switch a transistor is set at the atomic level by the atoms involved - and has nothing to do with the size of the transistor. The efficiencies in design of a transistor in terms of size and power can only approach the electronic excitation energy levels. So basically speeds of silicon P/N transistors have an upper limit which we are basically at, and making them smaller in terms of nanometers sizes for the junctions, isn't going to change that. Over the years overhead to get close to the energy levels have been removed.
However... they are still making the transistors physically smaller, so more on each chip, and less power to switch them. Hence performance can increase by making as many things 'parallelised' as possible. CPUs can only go parallel by adding cores/threads. GPU's however do set tasks, almost down to set task per pixel per polygon/pixel/whatever. Hence they can be made in huge parallel groups. So for example a 2080 down to a 2060 mostly have the same actual clock speeds, just the 2080 has way more cores. And we are talking hundreds /thouands of shader cores, mapping units, more tensor cores, etc. etc. etc. GPUs can probably keep growing to the point where the core count approaches the pixel count without the need for transistors to get faster.
The two main issues with CPUs is two-fold:
*Much if not most* of the performance optimization that *can* be done with CPU architecture *has* been done. There are 1000's of tiny little optimizations that go into making the pittance additional IPC gains we get these days. That's the main reason why companies have stopped trying to go much faster as well: a good chunk of the die space in a modern CPU is dedicated to error detection/correction. The faster you go, the more of the die you have to dedicate to it, and the lower your yield per wafer. That's why AMD and even Intel have been trying to get companies to optimize for larger core counts. Even now, they're relying on speculative execution, which continually shows serious security problems (like the exploit showed for AMD Bulldozer and newer I caught in my news feed today). Nobody'd be doing that if they had other ways of speeding things up.
Power consumption is now a major selling point, so companies have been encouraged (for battery life reasons in laptops/phones, and Cost/Environmental reasons in Server applications), so neither Intel or AMD have taken the 'eh, throw wattage at it'. And the issue with Silicon is, you can only do that so much anyway, even with a phase-change cooler or LN2
GPUs have gone through leaps and bounds because the GPU's workload can be parallelized far more then the CPU's, so increases in the processing power of each Cuda core/Compute unit is also met with simply having more of them, a LOT more, and more efficient parallelizing circuitry to spread the load better.
remember kids, IPC isn't real and every application is optimized for low thread counts
The fact is that Intel pushed the desktop 4c8t mantra for so long it locked desktop software into a sinkhole of singlethreadedness, and the past 3&1/2 years of ryzen has only just begun to break the stranglehold.
Clock rates for silicon won't get much higher without some insane breakthrough on a physical chem level, and IPC gains will only go so far. The far future of silicon lies in heavy multithreading and increasing power efficiency/transistor density to achieve mondo coars on the desktop.
"As a result, my 12 year old comp has better single core performance than the ryzen 2700x" Nope. Newer architectures execute more instructions *per clock cycle*. They call this idea "IPC uplift" (instructions per clock). If it worked the way you are thinking, PrescHOT processors would still rule the roost in single threaded performance.
Right, so Intel is faster, in number of workloads or specifically games. Important to remember Spectre and Meltdown, branch prediction, and AVX512 among other things. AMD chose a more reliable part with fewer fault points. They haven't eliminated the faults of these issues nor added avx512, the question is a matter of Use Case more so than just give me features alone.
It would be nice to see AVX added and 32 pcie lanes on the 12 core AM4 Parts, because that's a lot of dough to spend on those parts. BTW Moore's law is nearly dead, and this is why they are focusing on Features, and additional Cores and other technologies are beefing up, such as PCIE 4 for example, or DDR 5 coming.
Don't let yourself burn out Steve. It's ok to take breaks.
The 20:06 gaming question was insightful.
Where might I find "chemically reactive contact paper" like you used in the video "Vega GPU Mounting Pressure Variance & Quality Control"?
I think you mean "pressure sensitive film"? Our lab guys use it to measure contact of feet on the floor and contact patches inside cadaver knees and stuff like that. I know Fuji makes some, I think we also use a 3M variant. Search for that term and it should pop up something similar.
I can only find Fujifilm Prescale, and that's pretty stupid expensive, and sold in more industrial quantities. I haven't looked at places like alibaba yet though.
@@d00dEEE Ya, that stuff. Thank you!
20:05
My 2 ¢ on this: I have observed it over the years, that developers simply do not care about optimization anymore. Like Steve said, the hardware can just brut force it, so why bother, eh? Back in the day, where the hardware was the limiting factor, there were all those nice tricks and 'somke and mirrors' used by devs, to get the look and the fluidity they needed for their game, on the hardware of the time.
No it's not an issue as much, so ... why bother? They just don't. That's why many games now run horrid compared to how they look.
Similar with other Software, too. My current Discord instance consumes 260MiB of RAM. That would have been an unbelievable amount of resource waste, back in the IM/IRC days.
I have to disagree. Game studios keep pushing themselves and the hardware to new limits, both because of competition and out of sheer enthusiasm for the art of making games. See what Guerilla did with Horizon Zero Dawn. Or look at the developments regarding PBR and what that meant for texturing and lighting and for the art pipeline as a whole. And if it's not graphics, it's AI, not only for enemy tactics but also for procedural environments and animation. And don't forget the huge difference between the quality of games at the beginning of a console's lifetime and at the end: the hardware hasn't changed (much), but the developers have learned to harnas the system and squeeze every bit of performance out of it.
For many reasons , your script / story abt growing, managing, and strategic-planning your utube biz
is up there with the best on cnbc and bloomberg
A question for Tin and Kingpin: What makes a good PBC for overclocking? Why are the EVGA Dark and Kingpin boards better for overclocking than "normal" PCBs? Additionally, how much of a difference does the PCB make compared to silicon lottery in performance, especially in terms of memory?
That's whats pretty brilliant about AMD's method of supporting a platform across so many generations. Once you are on the platform at any price point, providing a wide upgrade path will sell more chips. Between actually reasonable price reductions on older parts, and meaningful performance improvements between generations its kind of a win/win for them and the consumer. The 4790k is still stupid expensive for its age, and while I thought mine was dead (after being handed down to my kids) it turned out to be the asrock z97x motherboard (also what I felt was too expensive to replace). They got a B450 with my old R9 Fury and a 2200G and can get upgrades when I do.
his video looks so good in 1440p 60fps wowwww... great work
I am a HUGE fan of SFF systems (building one currently), and I would LOVE to see you do content on it, but I fully understand your viewpoint in why you won't cover it. I'll still watch all your videos though!
"I don't ever want to grow to that size too"
*crumples up resume*
GN will never need a guy to stand around and occasionally look busy. Dad was right again :(
One restriction of L2$ is the fetch bubble.
Modern branch predictors can memorize code paths that can't fit in L1$, but sit nicely in L2$. However if access to L2$ creates a fetch bubble too huge for the frontend to hide, the core would stall and the benefit of a huge branch predictor is lost.
Questions for manufacturers: how can the technology business be more insulated, mobile or modular, in order to withstand the problems that are occurring with the world wide outbreak of things like coronavirus. These are starting to come more often as our world wide integration increases across both technologies and social barriers.
20:55 They will go more real-tracing, easier from the dev perspective because no lighting issues in production because that effort slides to thew user (and their gpu), and that requires horsepower.
Hopefully it will go like the shaders, in ye olden days there were seperate vertex shaders and whatever the other ones were called, then it became just shaders, graphics cores can later on become a tad more versatile and all cores will be raytracing capable, which will probably aid gpgpu use on the desktop.
25:45 Better question is why no L4 for apu's? Really fast L4 to bridge ram and the gpu.
And if VR will spread more we need in future gpus capable of 4-8k res + raytracing and 90+fps (depending on headset) all the time. For that we will need insane compute power increase.
Great Steve@GN, thanks for all of the information. Awesome video :-)
Hearing what Logitech had to say about the G5 mouse makes me extra happy to have bought one a few months ago for 5 dollars.
The thing just sits in my hand so naturally and feels like it's built like a tank
Question for the overclockers. Regarding extreme overclocking (using LN2 or whatever), what do you see the point of it being? Aside from getting the biggest scores on some benchmark, how do you see this as helping with normal day to day usage, if at all?
AskGn: Are manufacturers going to start making fabs/expanding factories from china to taiwan in the future? (Mostly applies to dram factories as they seem to have had a higher demand than other products)
Question for Taiwan: for mini-ITX builds, there is a thread on smallformfactor[.]net suggesting a new format, Flex-ITX. How hard is it to alter existing formats of a motherboard? I would provide a link, but external links get deleted on youtube. The thread goes into great detail and I would love some more info from a manufacturers perspective.
I can't believe this channel is already at 5 people. That is crazy, I thought it was like 3 people in total.
Questions for ExtremeOC'ers: When trying to go for crazy high OCs on GPUs do you perform PCB modification often? Like replace smds, caps, or add additional power stages or do you just stick to GPUs like Kingpins or Hall of Fame cards.
Also, when you do modify the gpus what do you often try to fix? Power limits? Some weird stability issues? More Extreme OC limits?
Lastly, what's the coolest or craziest mod you have done?
Thank you.
I can chip in for CPU overclocking a moment.
Most insane thing I've done with my old 4790k: I delided it and cooled it with a somewhat DIYed two stage refrigeration system. It held down the CPU to -70C under full load. Got some sweet scores from it.
The second stage of the cooler ran on ethylene, without load you could go down to -100C :D
This setup would also work for GPUs, it just would be freaking huge!
Thank you so much for your effort to eliminate those single use plastic bags! And also talking about it. Lets keep working on raising awareness, and get people to consider that seemingly small things can add up to huge differences in the long run. I look forward to a day that if an average consumer opens a product, that if ecologically irresponsible practices are used, that average consumer rethinks supporting those products/businesses. Once again, you made another great video, keep up the great work.
Question for kingpin or any other Overclcoker..........Is there a way to get AMD's PBO to boost higher? Perhaps in some wierd AMD CBS settings in the BIOS?
Buildzoid recently did some videos on how to "Maximise Ryzen performance the lazy way" on a couple of motherboards, those did include PBO IIRC.
ColtaineCrows yeah I saw them,but even he says that PBO scalar does nothing and that you can't really get higher than the stock boost levels,which sucks....just wanna actually OC these ryzen chips,I may have to just build me a Roboclocker or something
Do you mean what this Ryzen 5 3600 is doing ? th-cam.com/video/lXXq4us-51g/w-d-xo.html
Question for Experienced Overclocker: Is there a way around the inability to set max adaptive vcore voltage below spec in X299 BIOS? As an example, with my 9980XE I'm stable at 4.5GHz all core at 1.15v, but I have to set voltage control to Manual in order to achieve that voltage - with Adaptive or Offset voltage control, it's forced to about 1.23v regardless of what I set as max voltage. My motherboard is specifically the Asus ROG Rampage VI Extreme Omega.
Damn, would've liked to see you tackle SFF again. Not sure if you really like this solution to it, but this is what I'd like to see from SFF reviews:
The best cooling possible. In SFF builds, your challenge isn't "how much hardware do I have to buy to make this hardware cooled" like in ATX builds. Even in the walmart case, if you put 3 rads in there, it'd probably be fine. But in a Dan Case, you can't do that. The limitation is the case. So I want to know before I buy: what's the most I can get away with putting in here? So a standardized set of hardware (at least cooling) doesn't work. Sometimes you need a 120 or 240 AIO. Sometimes you can't do that, and need a low profile downdraft cooler. Sometimes you can fit a long GPU, sometimes you can only go half length. Sometimes even a blower makes the most sense. I like to see the "best" config, and know "if I dump in the money for cooling, what can I fit in here"?
Question for Kingpin / Overclockers: What has been the hardest thing for motherboard manufacturers in the past, and going forward, when it comes to overclocking: physical components and layout/connections versus BIOS capabilities? And why?
Steven Gibson,
Raytracing will be pushing graphics developmemt for the foreseeable future. The goal is for all lightning, shadows and reflections/refractions to be raytraced to achieve actual global illumination.
Currently we only have limited raytraced lighting and even then we need de-noising, as we have too few rays.
Question: As a customer we see all these channels giving us a value per performance rating for components they test. That is why the 3600 is so highly rated. However, I find that there is a lack of a measurement that includes where you coming from. Like: How much extra performance do you gain from the system you are coming from. It would be really cool if some kind of archetype systems of older age could become part of the calculation. Couldn't we do something like: "Hey, if you come from an intel3570, buying a ryzen3600 would give you X amount of performance increase, and this offset between the two is then broken down in $ per performance increase. This would be a really cool sheet to check for when considering an upgrade. It basically would help you determine how much real performance gain per money you would gain for your upgrade.
I heard BZ say he had a chip hit 4.75GHz with PBO. The workload was flinging his mouse cursor around the desktop, though.
May I ask.. what is PBO? Ty
@@Akkbar21 his chip does not seem to hit higher max clocks when using pbo, it just improves the average clock speed (he has a 3700x and a 3950x) my 3600 can get higher clock using pbo, but when i tried it i had stability issues, but the bios has had a lot of updates since and i have not tested it since
@@Akkbar21 precision boost overdrive
What settings do most novice overclockers overlook that can actually make a large difference?
Definitely want a full copper mug, please bring it back! I regret not buying one when they were available.
Question for kingPin: can 6Ghz overclock be achieved with ambient cooling by disabling hyperthreading and a number of cores(1-7) on a 9900K/KS?