Sequential Logic in HDL

In this lesson, we will look at how to represent very simple sequential logic in Verilog. We'll use the 'reg' component to implement our Flip-Flops and use always@ syntax to trigger our Flip Flop on either the rising-edge, falling-edge, or both, of the clock.

[@juliuscesar4176]

You are a lifesaver. You helped me finish my digital logic lab final course project. Everything compiles, runs, and I have waveforms. I know this is simple to you but I am just a beginner and it's still white magic to me. Respect.

[@vickymoreno3977]

Thank you so much! I have a HDL exam this Thursday, this video really helped.

[@adnanmutlu1972]

visual studio code stopping working for no reason is the most relatable thing to happen to any programmer :')

[@petercheung63]

thank you Derek

[@anjalin7935]

Could you please put the link for the 'sequential logic representation videos' you were talking about?

[@thomasdeniffel2122]

Look at his uploads. Here it is: th-cam.com/video/nuuKhVsOJCE/w-d-xo.html

[@bluekeybo]

You should use non-blocking assignments inside an always@(posedge CLK) block

[@pratyushsrivastava83]

Could you explain how would that be better than using blocking assignments? I mean I have been told to use non-blocking assignment blindly but why?

[@yung_broccolini]

@@pratyushsrivastava83 general rule: non-blocking assignment in sequential blocks (e.g. always@(posedge clk)) and blocking assignments in combinational (non-sequential) blocks (e.g. always@(*) or using assign)
The idea is that non-blocking assignments are all executed simultaneously, so if your sequential block has some specific timing, you want to make sure that your assignments are happening all at the same time, not staggered.
In combinational block, that doesn't matter because timing isn't a concern