State Machines - coding in Verilog with testbench and implementation on an FPGA

Finite state machines are essential tool hardware and software design, but they are actually quite simple to understand. We walk through 1) What is a finite state machine?, what is the difference between a Moore and Mealy state machine? 2) How to design a state machine, 3) How to code a machine in Verilog.
We will be using the example of a simple pair detector, but the principle can be applied for any state machine.

[@venkatreddy5964]

I was really helpful, Even our professor wasn't much perfect, thank you sir and keep doing this kind videos it would be much helpful one again tank you sir 👌👌

[@matinfazel8240]

Thanks for sharing your useful knowledge!

[@barsmertakpnar3136]

Very clear and understandable video thanks for informing us about fsm's

[@TymexComputing]

13:45 - thats the question i was asking myself for 13 minutes :), so many state machines to consider :)

[@i-manuel271]

This was a great video!!

[@GeorgeAlbercook]

Strictly speaking it seems like the second and third zeros are also a pair. This is a detects something but you don't know if it is pair or triplet.

[@shamilniftaliyev]

You are the king!

[@dansylee1]

I see that in the verilog code above, detect is a flopped version of (state == 2'b11); thus, the signal tap does show that detect is asserted 2 clk cycles after consecutive 0’s or 1’s of inbits.

[@InfiniteNesLives]

There is a problem where your state machine doesn’t detect the second pair when there’s 3+ matching sequential inputs.

[@harithabandara3212]

thank you!

[@TonyDaExpert]

Thank youuuuuuuuuu

[@athuldas44]

What is inbits that was shown in first program

[@ngochuy7683]

thank you so muchh!!

[@AkbarRajaei]

good job.

[@valeriegirrens4715]

When I navigate to netlist viewer none of the options are available, what do I do to fix this?

[@deeps474]

thanks!

[@AhmadTalkss]

im still confused how youre getting the 1s and 0s and which one they belong to

[@AhmadTalkss]

whats the difference between synchronous and asynchronous?

[@riddhisingh338]

Why wouldn’t you zoom in your test bench??

[@vaibhavbhasin1221]

ERROR ! great but some typo is there. 4:51 complete verilog for states, in state 1

[@VarshithaAS-PSEC]

Please Explain the test bench in briefly

[@VisualElectric_]

Please check out my other channel for longer form/tutorial FPGA content th-cam.com/channels/8gZeNz015waiQN5_-jvj7g.html