System Verilog: Sequential Logic and D-Type FlipFlops

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  • เผยแพร่เมื่อ 28 ส.ค. 2024

ความคิดเห็น • 2

  • @migry
    @migry 2 ปีที่แล้ว

    I’m pleased to see that you have setup and hold time on din (a critical piece of knowledge), but you show your output changing immediately after the rising edge of clock.

  • @bennguyen1313
    @bennguyen1313 ปีที่แล้ว

    Is it best to use a fast clock in an always block, and then sample the slower levels of the input signals.. or should you the input signals themselves in the sensitivity list?
    For example, if you want to do some behavioral code at the rising and falling edge of a signal, the I assume then one MUST use a fast clock (since you can't have an always block with both the posedge and negedge of the input signal)?