hi, great video, but was this also an opportunity (perhaps on the end) to show how a generate block will work. something like: genvar idx; genvar idy; generate for (idx = 7; idx >=0; idx = idx-1) for (idy = 3; idy >=0; idy =idy-1) begin assign D[idx * 4 + idy] = W[idx + 4] & W[idy]; end endgenerate
Don't know why he changed his initial "endian-ness" of the decoder. The LSB should be the 0-bit, e.g. for the 1-to-2 decoder if A = 0, then D0 = 1, and D1 = 0 (if D0 is the LSB) -- that is the correct convention
hi, great video, but was this also an opportunity (perhaps on the end) to show how a generate block will work. something like:
genvar idx;
genvar idy;
generate
for (idx = 7; idx >=0; idx = idx-1)
for (idy = 3; idy >=0; idy =idy-1)
begin
assign D[idx * 4 + idy] = W[idx + 4] & W[idy];
end
endgenerate
wolf
man you are great
what program are you using to draw the design in the beginning of this lesson?
It is OneNote
at 10:25 you did D3, D2, D1, D0 sequence but everything before was in opposite order (D0, D1, ...., D31)
why :(
hello, can I know where u have initialized W for wire in the code?
in a quaternary to binary decoder, how can negative input be implemented in verilog?
Don't know why he changed his initial "endian-ness" of the decoder. The LSB should be the 0-bit, e.g. for the 1-to-2 decoder if A = 0, then D0 = 1, and D1 = 0 (if D0 is the LSB) -- that is the correct convention
what are "Rnumber"s?