VHDL Lecture 16 Making Sequential Circuits

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[@siboushicham6207]

cristal clear,all respect and the best wishes
for your efforts

[@MaGra1959]

Great lecture again! Very clear!
I love these code examples and to see what hardware they produce.
Do you also have a script of your lectures as a pdf file or can you share your PowerPoint presentation?
Greetings from Germany :-)

[@EDUVANCE]

Thank you.
We are working on the documentation. We will soon be sharing the link for the same.

[@JGunlimited]

nice!

[@ryanwwest]

I was actually wondering about 15:10, you said to not have else statements after the (clk'event and clk='1') statement, right? So why are there else statements in this case? Thanks!

[@EDUVANCE]

The else statement is a part of if statement structure, which is written under the else if statement containing (clk'event and clk='1'). It is not the else statement for the outer if-else structure.

[@arijitbomber]

20:00 the clock is missing in the hardware diagram.

[@EDUVANCE]

One of the inputs to the Flipflops shown in the diagram is clock. Its an integral part of your flipflop design. The block diagram was displayed with focus to explain the two different hardware which are synthesized if we use a

[@awaisumar5125]

you have told many times that when we should not use Else statement under the clock...then why we are using it in our codes...we used it at 9:01 and also 13:45
please explain it

[@EDUVANCE]

The code you mentioned at 9:01 is as follows:
process (CLK)
begin
if (CLK'event and CLK ='1') then
if(RST = '1') then
Q

[@sravyareddy1477]

not only giving such a good explanation but also clarifying doubts includes much patience..thanks a lot
ur vedios are helping me a lot