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Glitch Free Clock Mux | Clock Mux | VLSI | What is Glitch Free Mux | GFCM | Circuit
Hi Everyone,
In this video, I have explained what is Glitch free clock mux, Why Glitch free clock mux is required, Why regular mux can not be used while switching clocks dynamically and How to design Glitch free clock mux.
Keywords:
Clock mux, Glitch free clock, glitch free clock mux structure, glitch free clock mux verilog code, glitch free clock mux circuit, glitch free clock mux design, How to design glitch free clock mux, what is glitch free clock mux, Dynamic clock switch, clock mux, multiplexer, 2:1 multiplexer, 2:1 mux, 2x1 mux, 2x1 multiplexer, VLSI, Verilog tutorial, Electronicspedia, Best VLSI channel, VLSI TH-cam channel, VLSI Design lectures, VLSI course, Verilog Tutorials, Basics of Verilog, Basics of System Verilog, Verilog coding, VLSI Design, VLSI Interview questions,
Chapters:
00:00 - Introduction
01:20 - What is Clock Mux?
03:40 - Why Regular 2x1 mux can not be used for clock switching?
05:54 - Glitch Free clock mux (GFCM) circuit
08:30 - GFCM waveform explained
#mux #multiplexer #clockmux #GFCM #2x1mux #VLSI #verilog
Credits:
1. A Magical Journey Through Space by Leonell Cassio | soundcloud.com/leonellcassioMusic promoted by www.free-stock-music.comCreative Commons Attribution-ShareAlike 3.0 Unportedcreativecommons.org/licenses/by-sa/3.0/deed.en_US
มุมมอง: 11 299

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ความคิดเห็น

  • @sali321
    @sali321 วันที่ผ่านมา

    Hi sir, If the first clk is double the time faster than the second clk, we are going to lose some data, how we can solve it?

    • @Electronicspedia
      @Electronicspedia วันที่ผ่านมา

      Hi, The two stage synchronizers as mentioned is used only when the source domain signal is quasi-static or stable for enough time. Here in this case there will not be any issue even if the clock frequency of source is double the destination But if the source signal changes before the destination samples it then this two stage synchronizers scheme cannot be used

    • @sali321
      @sali321 วันที่ผ่านมา

      @@Electronicspedia Thank you sir!

  • @mallikarjunb9901
    @mallikarjunb9901 2 วันที่ผ่านมา

    Why we use inverted clock for DLAT? Is it added to avoid delay?

    • @Electronicspedia
      @Electronicspedia 2 วันที่ผ่านมา

      No. It's added to make sure that we sample the enable only when clock is low to avoid the glitch.

  • @kirtikansal6946
    @kirtikansal6946 11 วันที่ผ่านมา

    perfect and easiest explaination please continue to add such experienced level topics, this help alot

  • @77uu22
    @77uu22 12 วันที่ผ่านมา

    Hi, One question on 2 flop synchronizer, the settling of metastability causes latency issue at the recever side, as for a signal changing from 0->1 at flop1 might settle to 1 or 0 before getting sampled by flop2, but will settle to value 1 in next clock So if it is settle in first clock the latency is 2 else the latency will be 3 How to update design to make this latency a fix value Considering both clock same frequency with phase difference

    • @Electronicspedia
      @Electronicspedia 12 วันที่ผ่านมา

      Hi, 2 flop synchronizer are typically used for quasi-static signals, meaning they will be high for enough cycles. In such cases the settling after one extra cycle should be fine. The destination might see a signal after 1 extra cycle. This is acceptable.

    • @77uu22
      @77uu22 12 วันที่ผ่านมา

      ​@@Electronicspedia Thank you Sir for your reply But if the destination is not able to tolerate this latency uncertainty even of 1 clock What can we do to provide fixed latency

  • @chimeziec4955
    @chimeziec4955 หลายเดือนก่อน

    Thanks a lot. You demonstrate thorough understanding and your efforts are much appreciated. However, your ads are a bit much. When the ads are too much, it affects focus.

  • @saipavanraj961
    @saipavanraj961 หลายเดือนก่อน

    GOOD EXPLANATION SIR WE NEED MORE VIDEOS ON CDC AND ALSO COME UP WITH LINT

  • @Kesavaa-nv3zs
    @Kesavaa-nv3zs หลายเดือนก่อน

    good explanation

  • @jamesbondgaming6901
    @jamesbondgaming6901 หลายเดือนก่อน

    Here we use same clk for both ff there cant be metastable state here

  • @adhavan.m411
    @adhavan.m411 หลายเดือนก่อน

    why the data transfer part is initiated in setup phase (second cycle) in timing diagram, actually it happened in the third phase only?

  • @Rehankhan-td7lz
    @Rehankhan-td7lz หลายเดือนก่อน

    TYSM❤

  • @srcreations8895
    @srcreations8895 2 หลายเดือนก่อน

    Hello sir, can I know what are the qualifications you have to teach this concept

  • @AkashSingh-dd2te
    @AkashSingh-dd2te 2 หลายเดือนก่อน

    RDC Issue is basically source reset to destination clock issue. It is related to reset assertion which means that if reset of source flop gets asserted and it causes input signal to destination flop change during aperture window of destination flop then that flop goes into metastability. The point here you are making is reset de assertion. Here, What happens is that if reset gets deasserted in the recovery - removal window of the flop, then it will cause metastability, which further means during that window period, reset signal should be stable. Yes, It can also cause destination flop goes into metastable state but It will be not be treated as RDC issue. This will be another form of CDC only. It can be taken using reset synchronization using reset synchronizers.

    • @Electronicspedia
      @Electronicspedia 2 หลายเดือนก่อน

      Agree to your points.

    • @Electronicspedia
      @Electronicspedia 2 หลายเดือนก่อน

      I have explained your points in the next video .

  • @mbreakn2620
    @mbreakn2620 2 หลายเดือนก่อน

    Not bad. Nice job!

  • @MidhunSasikumarpanangat
    @MidhunSasikumarpanangat 2 หลายเดือนก่อน

    may i suggest that you should add reset isolation techniques to the list of RTL methods. its a commonly used method

  • @travelfreakphani5933
    @travelfreakphani5933 3 หลายเดือนก่อน

    thanks sir !

  • @yarajanasaisindhuja5482
    @yarajanasaisindhuja5482 3 หลายเดือนก่อน

    Kudos to your efforts! 😊

  • @manpreetkaurjaswal1175
    @manpreetkaurjaswal1175 4 หลายเดือนก่อน

    what would happen in case of synchroniser fix if rstn2 signal changes while we are recieveing data in synchroniser from reset domain 1

  • @manpreetkaurjaswal1175
    @manpreetkaurjaswal1175 4 หลายเดือนก่อน

    why is the double synchronizer out in Reset domain 2; shouldn't we send synchronised output from domain1 itself?

  • @Vidyashreers
    @Vidyashreers 4 หลายเดือนก่อน

    Great explanation!!

  • @bsrinivasarao8622
    @bsrinivasarao8622 4 หลายเดือนก่อน

    LATCH WILL HAVE INPUT AS CLOCK ?? IS IT CORRECT ?

    • @Electronicspedia
      @Electronicspedia 4 หลายเดือนก่อน

      Latch will not have clock pin, it will have enable pin. But we are connecting clock to enable pin.

  • @bsrinivasarao8622
    @bsrinivasarao8622 4 หลายเดือนก่อน

    IS IT D LATCH OR D FF , AND WHERE IS THE INPUT FOR D LATCH , U HAVE APPLIED ENABLE AND CLOCLK TO ANOTHER INPUT , THEN HOW TO AND WHERE WE CAN APPLY INPUT????

  • @Anithachintala
    @Anithachintala 4 หลายเดือนก่อน

    Hi sir, you mentioned we will add 1 once pointers reaches to 7th location we compare MSB bits. Lets consider my both pointers are rolled overed onve so their msbs are 1 and if write pointer again reached to 7th location and read pointer is still at 0th location now when we compare msbs even if we add 1 to write pointer it will be still 1 and read pointer is also having 1 as msb due to previous full condition. Please clariy sir how to compare full condition in this case

  • @kamalapurammaheswar2854
    @kamalapurammaheswar2854 5 หลายเดือนก่อน

    is it possible to add half empty / hall full condition. if so how can we add that particular condition.

  • @sailakhaz8350
    @sailakhaz8350 5 หลายเดือนก่อน

    sir i have a doubt that the same binary to gray could be applied to the synchronous fifo or not

    • @Electronicspedia
      @Electronicspedia 5 หลายเดือนก่อน

      For synchronous fifo there is no need to convert from binary to gray

  • @sanskritisawant6161
    @sanskritisawant6161 5 หลายเดือนก่อน

    can someone help solve this question? FIFO DEPTH? Given Rules: i) A is input data and B is output data ii) frequency(clk_A) = frequency(clk_B) / 4 iii) period(en_B) = period(clk_A) * 100 iv) duty_cycle(en_B) = 25%

    • @Awakened_Pot
      @Awakened_Pot 4 หลายเดือนก่อน

      Found this in some book :) This can be solved by taking an example. Let the frequency of clk_B be 100MHz. That implies, frequency of clk_A = clk_B/4 = 25MHz Period of en_B = (1/25M) * 100 = 4 s As duty cycle of en_B is 25%, it will be high for a duration of 1 s. That means B receives the data for 1 s and will be idle for 3 s. Where as A sends the data every 0.04 s. So in 4 s it can transmit 100 words. And B receives 25 only, so we need to store the rest of 75 words in the FIFO. So the minimum size of FIFO required is 75 words.

    • @sanskritisawant6161
      @sanskritisawant6161 4 หลายเดือนก่อน

      @@Awakened_Pot Thank you!

  • @BhuvanaP-c4j
    @BhuvanaP-c4j 5 หลายเดือนก่อน

    Thank you

  • @Yen-TingChen
    @Yen-TingChen 5 หลายเดือนก่อน

    my hero

  • @pallakishoreyadav4537
    @pallakishoreyadav4537 6 หลายเดือนก่อน

    sir once the data enters metastable state it can settle to any value how can we ensure that we are sampling correct data at the 2nd flop

  • @shubhamshahi6280
    @shubhamshahi6280 6 หลายเดือนก่อน

    No clearity ,I am still confused.

  • @mejaeuk1104
    @mejaeuk1104 6 หลายเดือนก่อน

    감사합니다. Thank you!

  • @RandomHubbb
    @RandomHubbb 6 หลายเดือนก่อน

    not only deassertion! rstn1 could also assert at a point close to clock edge and flop2 can have metastability due do data change to 0 close to edge

    • @avvarutheja
      @avvarutheja 5 หลายเดือนก่อน

      Yes, this is the major problem. it happens only when aserting the rstn1. Hence some RDC checks are formed to make sure they are destination flop is protected from asyncronously resetting the source flop.

  • @Platica.Vasile
    @Platica.Vasile 6 หลายเดือนก่อน

    Thank you for the quick video, but for a more thoroughly you should corelate this with a timer to see exactly how the timescale affects the program.

  • @abdullahjhatial2614
    @abdullahjhatial2614 6 หลายเดือนก่อน

    what is difference between two flip flop and std double synchronizer ? they look similar in ciruit

  • @smitpatel7700
    @smitpatel7700 6 หลายเดือนก่อน

    awesome explanation!

  • @smitpatel7700
    @smitpatel7700 6 หลายเดือนก่อน

    can we add and gate to gate-off ren also ? like done on WR side?

  • @RandomHubbb
    @RandomHubbb 7 หลายเดือนก่อน

    2nd case is very confusing, i think it is a bad example to begin with. why would someone assert reset in domain 1 but then deassert reset in domain 2. what kind of functional use case is that to begin with?

  • @Shahidsoc
    @Shahidsoc 7 หลายเดือนก่อน

    light is in ur back, so shade come on board

  • @shreyagupta5742
    @shreyagupta5742 7 หลายเดือนก่อน

    Very well explained! Thank you

  • @Yemo_naniartsanddanc396
    @Yemo_naniartsanddanc396 7 หลายเดือนก่อน

    Good explanation🎉

  • @danielarthur7739
    @danielarthur7739 7 หลายเดือนก่อน

    I have a question, Im using clock gating in my design. My question is: the clock gating should affect the dual flop synchronizer or the synchronizer must have the free clock always?

  • @rohanyadala9096
    @rohanyadala9096 8 หลายเดือนก่อน

    Super..

  • @ytaccount9420
    @ytaccount9420 8 หลายเดือนก่อน

    For fast to slow, using toggle sync solution, how do we calculate the min cycles to be allowed before we can safely detect next pulse? Is it 4 (toggle ff- 1, double sync -2, d ff -1)? But toggle ff is triggered by clkA, so kinda confused How to calculate safe frequency of pulse

  • @kpark5467
    @kpark5467 8 หลายเดือนก่อน

    Nice explanation, Thank you. How do you set SDC constraints for CDC on 1st_flop and 2nd_flp ? and what else SDC do I need to set ?

  • @DeveshJani
    @DeveshJani 8 หลายเดือนก่อน

    Sir what to do if we have to apply clock domain crossing and reset domain crossing together?

  • @docvedios1955
    @docvedios1955 8 หลายเดือนก่อน

    Simply outstanding, got perfect picture on the topic. Thanks a lot

  • @ahyungrocks5509
    @ahyungrocks5509 9 หลายเดือนก่อน

    Great easy to follow series!

  • @bhargavchiru6002
    @bhargavchiru6002 9 หลายเดือนก่อน

    what have you studied ?

  • @nenadmilutinovic4752
    @nenadmilutinovic4752 9 หลายเดือนก่อน

    Hello Sir, what will 15.5 be rounded off to? 16 or 15? Thank you in advance!

  • @harshitha-8256
    @harshitha-8256 9 หลายเดือนก่อน

    I found the video extremely useful for my interview preparation, Thank you!

  • @akshaykumarmane1527
    @akshaykumarmane1527 9 หลายเดือนก่อน

    its very useful. please provide something on power domain crossing