I think the reason for keeping two flops closer in 2 flop synchronizer is to reduce wire delay so we get maximum time to resolve metastability and settle to stable value, you were mentioning reason is metastable signal will decay and disappear that part I did not get.
Yes exactly, if they are separated apart then the data signal might get corrupted because of wire length. It adds the delay. We may not be able to sample the signal at desired frequency.
I have a question, Im using clock gating in my design. My question is: the clock gating should affect the dual flop synchronizer or the synchronizer must have the free clock always?
Sir, I am a little bit confused about you tell us that two flops should be closer to each other to avoid getting the wrong output. But sir I think the clock is the only one responsible for this, because of the small delay of the path nothing will happen!!!!! That delay is for sure will be less than clock period???
Hi, When I mention the distance between two flops should be closer to reach other is actually we should be using standard cells, which are nothing but .lib cells or library cells for which there will be a timing spec available. If the Frequency of sampling domain is higher, we might end up in sampling wrong data, in such conditions we should go for 3 or 4 flops based standard synchronizer cells.
Hi Srinu, signal might go into metastable state on 1st FF, but eventually 2nd flop may not see the this as the signal gets settled to a stable value. This is true for upto certain frequency. But for high speed clocks say above 2GHz, 2nd FF also might go into metastability, in such cases 3rd stage FF synchronizer is required.
@@Electronicspedia Hi sir, how can we ensure that the stable value after metastable state from 1st flop is the correct data that is settled to a stable value. There might be a chance that the data may be corrupted after metastable state and the same data is captured by the 3rd ff?
Hi, yes whatever you told is correct, there might be a chance that data may be still on metastable condition even after 2nd stage, Usually this information comes from .lib characteristics of synchronizer. There will be some range of frequency information will be provided upfront, there will be a maximum frequency of operation below which the two stage synchronizer will be able to sample data properly, but if it sampling frequency crosses the limit, it might enter metastability. In such cases we may have go for 3 stage or even higher stage synchronizer. Hope this is clear.
Hi Prem, No. Of Flops in the synchronizer depends on metastability, i.e. what is the frequency of sampling domain or destination clock freq and also on the frequency of data rate change and how these standard cell synchronizers are modelled in each technology nodes.
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sir once the data enters metastable state it can settle to any value how can we ensure that we are sampling correct data at the 2nd flop
I think the reason for keeping two flops closer in 2 flop synchronizer is to reduce wire delay so we get maximum time to resolve metastability and settle to stable value, you were mentioning reason is metastable signal will decay and disappear that part I did not get.
Yes exactly, if they are separated apart then the data signal might get corrupted because of wire length. It adds the delay. We may not be able to sample the signal at desired frequency.
Nice explanation, Thank you. How do you set SDC constraints for CDC on 1st_flop and 2nd_flp ? and what else SDC do I need to set ?
I have a question,
Im using clock gating in my design. My question is: the clock gating should affect the dual flop synchronizer or the synchronizer must have the free clock always?
Here we use same clk for both ff there cant be metastable state here
Super..
Sir, I am a little bit confused about you tell us that two flops should be closer to each other to avoid getting the wrong output. But sir I think the clock is the only one responsible for this, because of the small delay of the path nothing will happen!!!!! That delay is for sure will be less than clock period???
Hi, When I mention the distance between two flops should be closer to reach other is actually we should be using standard cells, which are nothing but .lib cells or library cells for which there will be a timing spec available.
If the Frequency of sampling domain is higher, we might end up in sampling wrong data, in such conditions we should go for 3 or 4 flops based standard synchronizer cells.
sir as the signal is altered in first ff How can we ensure that we get correct output after 2nd ff
Hi Srinu, signal might go into metastable state on 1st FF, but eventually 2nd flop may not see the this as the signal gets settled to a stable value. This is true for upto certain frequency.
But for high speed clocks say above 2GHz, 2nd FF also might go into metastability, in such cases 3rd stage FF synchronizer is required.
@@Electronicspedia Hi sir, how can we ensure that the stable value after metastable state from 1st flop is the correct data that is settled to a stable value. There might be a chance that the data may be corrupted after metastable state and the same data is captured by the 3rd ff?
Hi, yes whatever you told is correct, there might be a chance that data may be still on metastable condition even after 2nd stage,
Usually this information comes from .lib characteristics of synchronizer. There will be some range of frequency information will be provided upfront, there will be a maximum frequency of operation below which the two stage synchronizer will be able to sample data properly, but if it sampling frequency crosses the limit, it might enter metastability.
In such cases we may have go for 3 stage or even higher stage synchronizer.
Hope this is clear.
thanks sir !
Good explanation
Thank you 😊
No clearity ,I am still confused.
Can you Suggest book for this
I am not aware of any books as such. But you can definitely refer to papers from Sunburst design they are really great.
@@Electronicspedia thbk you sir
@@Electronicspedia means CDC is not present in standard textbooks?
How we can calculate number of flops in synchronizer
Hi Prem, No. Of Flops in the synchronizer depends on metastability, i.e. what is the frequency of sampling domain or destination clock freq and also on the frequency of data rate change and how these standard cell synchronizers are modelled in each technology nodes.
@@Electronicspedia Thanks you sir responding to me, Keep doing more videos, I will also share your videos in my circle
@Prem Kumar Thank You for your Support. 👍
Nice explanation
Thank you 😊