Worst case is Write side is at maximum and read side is minimum. Based on this we have to calculate depth. Here in 160 clock cycles of writes, how many reads will happen should be subtracted from 160 160-(160*8/10) = 32
In FIFO depth calculation, if the burst size is not given, the read is continuous, then how we can calculate depth Eg: if 8 bit FIFO where it has wr_clk is 50 MHz and Rd_clk is 20 MHz, How we can calculate the depth of FIFO
Hi Prem, if FIFO wr_clk is more than rd_clk and burst size is not known or indefinite then fifo is going to overflow. In order to fix this we may have to back pressure the write side if FIFO becomes full.
Hi, In an ideal scenario since read frequency is twice write frequency we should be able read out all the data with 1 deep FIFO. BUT async FIFO involves synchronization of write and read pointers in order to calculate FIFO full and empty condition. Now if synchronization is done using 2 stage synchronizers then we might need 3 deep FIFO, assuming metastability settles in 2 clock cycles. But if metastability settles in 2+1 clock cycles then 4 deep would be safer. PS: here 100 MHz clock can also be out of phase wrt 50mhz clock Please share your thoughts.
can someone help solve this question? FIFO DEPTH? Given Rules: i) A is input data and B is output data ii) frequency(clk_A) = frequency(clk_B) / 4 iii) period(en_B) = period(clk_A) * 100 iv) duty_cycle(en_B) = 25%
Found this in some book :) This can be solved by taking an example. Let the frequency of clk_B be 100MHz. That implies, frequency of clk_A = clk_B/4 = 25MHz Period of en_B = (1/25M) * 100 = 4 s As duty cycle of en_B is 25%, it will be high for a duration of 1 s. That means B receives the data for 1 s and will be idle for 3 s. Where as A sends the data every 0.04 s. So in 4 s it can transmit 100 words. And B receives 25 only, so we need to store the rest of 75 words in the FIFO. So the minimum size of FIFO required is 75 words.
Thanks Sir,
Please ese hi videos bnate rhiye,
These are so much helpful.
Thank you. Sure will do more such videos.
Nice Explanation sir.
Thanks.
Thank you 🙂
awesome sir, great explaination
How did you arrived to 20 clock cycles of randomization ? Is it subtracted from 100clocks - 80 bytes of data ?
In case 1 why is the write time 200ns and not 180ns, as we are idle in the first 20ns ?
Obviously , i have the same question, why is it not 180ns in the first case?
Hey thanks for pointing it out, you are right it should be 180ns in case 1.
Hey thanks for pointing it out, you are right it should be 180ns in case 1.
Thanks a lot please give more variations Sir.
Hi, I have covered two scenarios in my previous video, please do check it out.
Thanks.
Sir, u mentioned to take worst case scenario so we should get FIFO depth = 160-(200*8/10) = 0
Worst case is
Write side is at maximum and read side is minimum. Based on this we have to calculate depth.
Here in 160 clock cycles of writes, how many reads will happen should be subtracted from 160
160-(160*8/10) = 32
minimum is 180 cycle to write 160 data, you can't ignore the initial 20 cycles in 3rd case
you can ignore the last 20 idle cycles, but not the initial 20 idle cycles
Yes that's correct
In FIFO depth calculation, if the burst size is not given, the read is continuous, then how we can calculate depth
Eg: if 8 bit FIFO where it has wr_clk is 50 MHz and Rd_clk is 20 MHz, How we can calculate the depth of FIFO
Hi Prem, if FIFO wr_clk is more than rd_clk and burst size is not known or indefinite then fifo is going to overflow.
In order to fix this we may have to back pressure the write side if FIFO becomes full.
Hi,
why didn't you ignore the first idle cycle in 1st case and why did you ignore the first idle cycle in 3rd case
In the 1st case also the idle cycle should be ignored. That was a mistake from my side.
I need 1920 data which is for write and 240 data which is for read, that means 8 bit write and 64 bit read for that this calculation is ok.
What should we do if read clock frequency is 100 MHZ and write clock is 50MHZ
Hi, In an ideal scenario since read frequency is twice write frequency we should be able read out all the data with 1 deep FIFO.
BUT async FIFO involves synchronization of write and read pointers in order to calculate FIFO full and empty condition. Now if synchronization is done using 2 stage synchronizers then we might need 3 deep FIFO, assuming metastability settles in 2 clock cycles. But if metastability settles in 2+1 clock cycles then 4 deep would be safer.
PS: here 100 MHz clock can also be out of phase wrt 50mhz clock
Please share your thoughts.
can someone help solve this question? FIFO DEPTH?
Given Rules:
i) A is input data and B is output data
ii) frequency(clk_A) = frequency(clk_B) / 4
iii) period(en_B) = period(clk_A) * 100
iv) duty_cycle(en_B) = 25%
Found this in some book :)
This can be solved by taking an example.
Let the frequency of clk_B be 100MHz.
That implies, frequency of clk_A = clk_B/4 = 25MHz
Period of en_B = (1/25M) * 100 = 4 s
As duty cycle of en_B is 25%, it will be high for a duration of 1 s. That means B
receives the data for 1 s and will be idle for 3 s. Where as A sends the data every 0.04
s. So in 4 s it can transmit 100 words. And B receives 25 only, so we need to store the
rest of 75 words in the FIFO.
So the minimum size of FIFO required is 75 words.
@@Awakened_Pot Thank you!