Thank you Anil, thanks for showing support. I will try to cover Spyglass Lint, this will be more from tools and error ruleset. There is not much from technical concept wise.
The Q of the flops cannot be "1" when reset is asserted. It will reset to 0. You need to connect the Q-bar to the D and take the Q-bar of synchronizer to the rest of the fanout.
Hi, since this is active high reset synchronizer, we want the synchronizer output to be 1 when reset is asserted, that's why the flop output should be 1. Here flop will be set when reset is asserted.
@@Electronicspedia Sir, but doesn't active high reset mean the flop will be reset for logic 1 and active low reset mean the flop will be reset for logic 0?
@@Anonymous-nq6ux yes your understanding is correct. But the reset value of the flop can be 0 or 1 based on flop type. We can have 4 combinations 1. Active high reset with reset value 0 2. Active high reset with reset value 1 3. Active low reset with reset value 0 4. Active low reset with reset value 1 Here i am referring to 2nd combination
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can you di the videos on spy glass lint sir?
Thank you Anil, thanks for showing support. I will try to cover Spyglass Lint, this will be more from tools and error ruleset. There is not much from technical concept wise.
Thanks for your reply.
When the reset is 0, output changes according to clock
if clock is drawn along with reset, it would be easy to understand
Explanation is very good, Can you make videos on RDC and ASYNCHRONOUS FIFO
Thank you Vineeth. Sure will cover those soon.
Thank you
The Q of the flops cannot be "1" when reset is asserted. It will reset to 0. You need to connect the Q-bar to the D and take the Q-bar of synchronizer to the rest of the fanout.
Sir, Thank you for the videos on CDC...
Just a small doubt sir.. shouldn't the output become zero when we apply reset?(@ 6:50)
Hi, since this is active high reset synchronizer, we want the synchronizer output to be 1 when reset is asserted, that's why the flop output should be 1.
Here flop will be set when reset is asserted.
@@Electronicspedia Sir, but doesn't active high reset mean the flop will be reset for logic 1 and active low reset mean the flop will be reset for logic 0?
@@Anonymous-nq6ux yes your understanding is correct.
But the reset value of the flop can be 0 or 1 based on flop type.
We can have 4 combinations
1. Active high reset with reset value 0
2. Active high reset with reset value 1
3. Active low reset with reset value 0
4. Active low reset with reset value 1
Here i am referring to 2nd combination
@@Electronicspedia Acha, okay sir, Thank you!
@@Electronicspedia I think when the reset value is equal to 1 it is called Preset regardless of being active high or active low, isn't that right ?
when can we expect RDC videos
Planned for this weekend. 👍