Hi, can you please draw timing diagrams to indicate what happens when reset is de-asserted during recovery or removal time? That will help in better understanding of concept.
I agree with you RDC assertion is problem if there are two resets, the destination is de-asserted and source is going under reset. But de-assertion of reset is also a problem when reset is not not de-asserted synchronous to clock. I think my message was not conveyed properly. I will put a note in description
Yes, this is the major problem. it happens only when aserting the rstn1. Hence some RDC checks are formed to make sure they are destination flop is protected from asyncronously resetting the source flop.
RDC Issue is basically source reset to destination clock issue. It is related to reset assertion which means that if reset of source flop gets asserted and it causes input signal to destination flop change during aperture window of destination flop then that flop goes into metastability. The point here you are making is reset de assertion. Here, What happens is that if reset gets deasserted in the recovery - removal window of the flop, then it will cause metastability, which further means during that window period, reset signal should be stable. Yes, It can also cause destination flop goes into metastable state but It will be not be treated as RDC issue. This will be another form of CDC only. It can be taken using reset synchronization using reset synchronizers.
@@Electronicspedia when rstn1 is asserted and rst2 is not in active state , so output of first flop can change to zero independent of the clock . Which can propagate to input of second flop and can cause the metastability . This is the RDC .
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Hi, can you please draw timing diagrams to indicate what happens when reset is de-asserted during recovery or removal time? That will help in better understanding of concept.
Sure I will explain in detail in my next video. Thanks for suggestions. 👍
RDC is assertion issue not the de-assertions. and also if you can cover reset ordering as one of the techniques to solve the RDC.
I agree with you RDC assertion is problem if there are two resets, the destination is de-asserted and source is going under reset.
But de-assertion of reset is also a problem when reset is not not de-asserted synchronous to clock.
I think my message was not conveyed properly. I will put a note in description
Hi,
Nice one. I've a question. Which is a best way for a DV engineer to verify the reset tree?
not only deassertion! rstn1 could also assert at a point close to clock edge and flop2 can have metastability due do data change to 0 close to edge
Yes, this is the major problem. it happens only when aserting the rstn1. Hence some RDC checks are formed to make sure they are destination flop is protected from asyncronously resetting the source flop.
RDC Issue is basically source reset to destination clock issue. It is related to reset assertion which means that if reset of source flop gets asserted and it causes input signal to destination flop change during aperture window of destination flop then that flop goes into metastability.
The point here you are making is reset de assertion. Here, What happens is that if reset gets deasserted in the recovery - removal window of the flop, then it will cause metastability, which further means during that window period, reset signal should be stable.
Yes, It can also cause destination flop goes into metastable state but It will be not be treated as RDC issue. This will be another form of CDC only. It can be taken using reset synchronization using reset synchronizers.
Agree to your points.
I have explained your points in the next video .
RDC is assertion problem and not the deassertion problem, please do correct
Would you please explain how RDC assertion is problem ?
@@Electronicspedia when rstn1 is asserted and rst2 is not in active state , so output of first flop can change to zero independent of the clock . Which can propagate to input of second flop and can cause the metastability .
This is the RDC .
Thanks 👍