In the STA nano book, I have seen a report that startpoint is UFF and endpoint is UAND. So when should we use ICG and when should we use only AND gates?
so from your example, what if the en signal is high in the mid of when clk is low? it will still cut the clock pulse right? I think you should be using ff instead of latch!
I think in the SystemVerilog code it should be if(clk) instead of if (~clk). This is because we're trying to infer a positive level triggered latch which is transparent during positive level and hence samples the input on the negative going edge.
Hi Ayush, No we should be sampling on the negative level triggered latch. Then only we ensure that enable signal is low when we AND with clk in subsequent AND gate
Latches are level triggered. So they wil be working as long as they levels are high or low depending on active low or active high triggered. If you use the Flip flop then you can sample the data input only on the clock edge.
@@ElectronicspediaGreat video very helpful for my digital electronic systems exam. Just one question. If we replace the latch with a D flip flop and we sample on the positive edge but with an inverted clock, is the same?
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Great easy to follow series!
In the STA nano book, I have seen a report that startpoint is UFF and endpoint is UAND. So when should we use ICG and when should we use only AND gates?
Why we use inverted clock for DLAT?
Is it added to avoid delay?
No. It's added to make sure that we sample the enable only when clock is low to avoid the glitch.
Very good content and explanation, thanks 😊
Glad you liked it 😊
Hello, your videos are very informative and useful.
Do you provide any sort of formal online RTL training also ?
Thank you Rajat, Glad you like the videos.
I do not have any online RTL training.
for SV we can use always_latch, right?
I didn't understand why Neg edge latch is chosen, it will work with Pos Edge latch as well right!
so from your example, what if the en signal is high in the mid of when clk is low? it will still cut the clock pulse right? I think you should be using ff instead of latch!
En signal is latched only when clock is low going to the latch, but at that time subsequent and gate won't propagate it to output as the clock is low.
I think in the SystemVerilog code it should be if(clk) instead of if (~clk). This is because we're trying to infer a positive level triggered latch which is transparent during positive level and hence samples the input on the negative going edge.
Hi Ayush, No we should be sampling on the negative level triggered latch. Then only we ensure that enable signal is low when we AND with clk in subsequent AND gate
@@Electronicspedia okay sir got it thanks👍
Very nice...
Why can't we use flip flops instead of latches
Latches are level triggered. So they wil be working as long as they levels are high or low depending on active low or active high triggered.
If you use the Flip flop then you can sample the data input only on the clock edge.
@@ElectronicspediaGreat video very helpful for my digital electronic systems exam. Just one question. If we replace the latch with a D flip flop and we sample on the positive edge but with an inverted clock, is the same?