Clock Domain Crossing (CDC) Basics | Techniques | Metastability | MTBF | VLSI Interview questions

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  • เผยแพร่เมื่อ 9 ม.ค. 2025

ความคิดเห็น • 20

  • @Electronicspedia
    @Electronicspedia  2 ปีที่แล้ว

    Please Like, Share and Subscribe to my channel th-cam.com/channels/3mTACG8vPWsHQFMfxzeDZg.html

  • @cyrillemagdi7717
    @cyrillemagdi7717 2 ปีที่แล้ว +3

    Thanks a lot for your amazing covering of the CDC topic.

  • @jogeshsingh854
    @jogeshsingh854 2 ปีที่แล้ว +2

    Good content regarding CDC by visual presentation 👍🏼👍🏼👍🏼 😊

  • @Naveenkumar-mj8eh
    @Naveenkumar-mj8eh 2 ปีที่แล้ว +1

    Good keep posting sta examples ,different concepts asked in interview with examples makes good content

    • @Electronicspedia
      @Electronicspedia  2 ปีที่แล้ว

      Thanka Naveen. Sure will cover all the topics in upcoming videos. Keep watching this space 🙂

  • @vikasbansal4180
    @vikasbansal4180 2 ปีที่แล้ว

    Amazing lecture, thanks sir

  • @ankitsingh-wg3cn
    @ankitsingh-wg3cn 2 ปีที่แล้ว +1

    Nice explanation Ravi

  • @srcreations8895
    @srcreations8895 4 หลายเดือนก่อน

    Hello sir, can I know what are the qualifications you have to teach this concept

  • @HDgaming345
    @HDgaming345 ปีที่แล้ว

    Hi. Nice video and explanation. Where is part 2?

    • @Electronicspedia
      @Electronicspedia  ปีที่แล้ว +1

      Here it is th-cam.com/video/fwh-KISWs7c/w-d-xo.html

  • @nikitajavali1055
    @nikitajavali1055 2 ปีที่แล้ว

    Good one👍

  • @pranavgupta4552
    @pranavgupta4552 2 ปีที่แล้ว

    Hi..
    If due to metastability wrong data is sampled by 2nd FF in double syncronizer , how to take care this situation.

    • @Electronicspedia
      @Electronicspedia  2 ปีที่แล้ว

      If 2nd FF goes into metastability then 3 stage synchronizers are required. Usually upto 1 GHz 2 stage synchronizers will work

    • @----700
      @----700 ปีที่แล้ว

      ​​@@ElectronicspediaI have a doubt regarding metastability. Please help me out.
      At 9:46 as sigA changes in setup-hold window of clkB , sigB becomes metastable. But isn't it sureshot that signal B will come out of metastability at next rising edge of clkB as input A doesn't change in the setup-hold window.
      Or is it possible that sigB remains metastable even after next rising edge of clkB. If yes then what's the reason?

  • @karthishanmugam5674
    @karthishanmugam5674 2 ปีที่แล้ว +2

    Hi sir,
    I have some doubts in MTBF,
    If tx is working with 1MHz and rx is working with 1GHz
    How many stages used in synchronisation for single bit transfer from tx to rx,with the help of MTBF
    Thanks for advance

    • @Electronicspedia
      @Electronicspedia  2 ปีที่แล้ว

      Stages of synchronization depends on tech node and it comes from library cell information.