Hi Sir, Your all videos are very good and clear explanations.can u please explain some micro-arch development and pcie protocol also its very helping us
IS IT D LATCH OR D FF , AND WHERE IS THE INPUT FOR D LATCH , U HAVE APPLIED ENABLE AND CLOCLK TO ANOTHER INPUT , THEN HOW TO AND WHERE WE CAN APPLY INPUT????
Here we are using clock as enable condition. Not as an actual clock. The basic difference is that it will sample the D input on the level signal of clk.
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Hi Sir,
Your all videos are very good and clear explanations.can u please explain some micro-arch development and pcie protocol also its very helping us
very useful for me
LATCH WILL HAVE INPUT AS CLOCK ?? IS IT CORRECT ?
Latch will not have clock pin, it will have enable pin. But we are connecting clock to enable pin.
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thankyou sir
nice. thank u sir
Glad you liked it. Keep watching and happy learning. 😊
IS IT D LATCH OR D FF , AND WHERE IS THE INPUT FOR D LATCH , U HAVE APPLIED ENABLE AND CLOCLK TO ANOTHER INPUT , THEN HOW TO AND WHERE WE CAN APPLY INPUT????
How is It a latch if we are giving it a clock ??
Here we are using clock as enable condition. Not as an actual clock.
The basic difference is that it will sample the D input on the level signal of clk.