Nice video - but there might be some inaccuracies at 15:38: While drawing the timing graphs, you are assuming the frequency of clkB matches clkA which is incorrect. doubleq and output of the last flop do not follow clkA frequency -> the pulse at the output of XOR should be as wide as the (timeperiod/2) of clkB. Is that correct?
There is no assumption of clkb freq same as clka. They can be completely asynchronous. Here just got drawing diagram i have considered the clocks same. But the logic still holds good.
Thanks, it was explained very nicely. I had a few doubts about this. what if we use a D FF at the source side, and the clk relationship of source and destination is not known as it can change in the later stage of the design. Considering the above constraints 1. for how many clock cycles should the signal be stretched so that it can be sampled at destination clock? 2. Will this technique work or we should go with a handshake-based mechanism?
For fast to slow, using toggle sync solution, how do we calculate the min cycles to be allowed before we can safely detect next pulse? Is it 4 (toggle ff- 1, double sync -2, d ff -1)? But toggle ff is triggered by clkA, so kinda confused How to calculate safe frequency of pulse
in the video at fast to slow concept in timing diagram the output of tff is initially zero and when the pulse arrives the output of tff qt should change at the same clock edge as the pulse arrives is that correct?
Hi Vinay, all the flip flops considered will sampling the signals on the active edge of clocks and these will be sequential elements hence the data will appear on the output in the next clock cycle. But however for waveform representation some people choose to draw it on the same clock.
Hai sir In slow to fast domain after using the dff(after 3rdff) we will generating pulse,but the generated pulse Frequency not same as the pulse frequency of domain A. This is correct??
Thanks for your reply.but in the domain B instead of AND gate (like edge detection) we used XOR.Why can't we use AND gate to generate the pulse instead of xor gate or else shall We use the AND gate?
XOR gate will generate a pulse in domain B, every time there is a pulse in domain A. Here the thing to be noted is on clock domain A, we are using T flip flop to generate the level signal. That's why we need XOR gate, if you use AND gate based edge detection technique we can detect only either posedge or negedge not both together. But with XOR gate we can detect posedge and negedge both.
No its correct, it will detect zero and thats why it will retain past value Qn which is 1 , so tq remains 1. (T flop toggles only if input is 1, if 0 it will retain Qn.
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GOOD EXPLANATION SIR WE NEED MORE VIDEOS ON CDC AND ALSO COME UP WITH LINT
Nicely explained, keep posting concepts related CDC techniques
Glad you liked. Thanks
I will post more videos on other concepts as well. Keep watching, happy learning.
Very well explained ! Thank you for the video.
Excellent explanation, can you post more videos on CDC as soon as possible
Hey thanks for feedback. I have covered basic CDC topics already, please take a look. Will cover more CDC and Reset Domain Crossing (RDC) soon.
@@Electronicspedia Waiting 🙏
very nice explanation thank you keep it up
Nice video - but there might be some inaccuracies at 15:38:
While drawing the timing graphs, you are assuming the frequency of clkB matches clkA which is incorrect. doubleq and output of the last flop do not follow clkA frequency -> the pulse at the output of XOR should be as wide as the (timeperiod/2) of clkB.
Is that correct?
There is no assumption of clkb freq same as clka. They can be completely asynchronous. Here just got drawing diagram i have considered the clocks same. But the logic still holds good.
Thanks, it was explained very nicely. I had a few doubts about this.
what if we use a D FF at the source side, and the clk relationship of source and destination is not known as it can change in the later stage of the design. Considering the above constraints
1. for how many clock cycles should the signal be stretched so that it can be sampled at destination clock?
2. Will this technique work or we should go with a handshake-based mechanism?
If clock relationship is unknown then it's makes sense to go with handshake based mechanism.
Nicely done Ravi ...carry on
Thank you 😊
Thank you, You are doing a great work
Thank you 😊
I couldn't find the edge detection technique video in your playlist sir could you please share the link if that video
could you also describe handshaking based circuit for fast to slow
Hi, I have explained in this video
th-cam.com/video/qDnWYp1nG9I/w-d-xo.html
This is handshake based synchronisation technique
sir could you please explain the issue of convergence,divergence and re-convergence with their solutions
good one sir
Thank you 😊
what is difference between two flip flop and std double synchronizer ? they look similar in ciruit
For fast to slow, using toggle sync solution, how do we calculate the min cycles to be allowed before we can safely detect next pulse?
Is it 4 (toggle ff- 1, double sync -2, d ff -1)?
But toggle ff is triggered by clkA, so kinda confused
How to calculate safe frequency of pulse
Thanks for the explanation
Thanks for the support. Keep watching Happy learning 👍
in the video at fast to slow concept in timing diagram the output of tff is initially zero and when the pulse arrives the output of tff qt should change at the same clock edge as the pulse arrives is that correct?
Hi Vinay, all the flip flops considered will sampling the signals on the active edge of clocks and these will be sequential elements hence the data will appear on the output in the next clock cycle.
But however for waveform representation some people choose to draw it on the same clock.
@@Electronicspediathankyou so much....
Hai sir
In slow to fast domain after using the dff(after 3rdff) we will generating pulse,but the generated pulse Frequency not same as the pulse frequency of domain A.
This is correct??
Yes you are correct. That is why we call it as clock domain crossing.
Crossing of signal/pulse from clock domain A to domain B.
Thanks for your reply.but in the domain B instead of AND gate (like edge detection) we used XOR.Why can't we use AND gate to generate the pulse instead of xor gate or else shall We use the AND gate?
XOR gate will generate a pulse in domain B, every time there is a pulse in domain A. Here the thing to be noted is on clock domain A, we are using T flip flop to generate the level signal. That's why we need XOR gate, if you use AND gate based edge detection technique we can detect only either posedge or negedge not both together. But with XOR gate we can detect posedge and negedge both.
@@Electronicspedia okk
Thank you so much for your well explanation.
Your Tq is wrong since TFF will also toggle the zero level after the PA pulse to '1' - check it
No its correct, it will detect zero and thats why it will retain past value Qn which is 1 , so tq remains 1. (T flop toggles only if input is 1, if 0 it will retain Qn.
light is in ur back, so shade come on board
Sir can u plz share your contact no. Or mail id so that I can send my requirements based on missing pulse detection