VHDL Lecture 23 Lab 8 - Clock Dividers and Counters

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[@sagarwaghmare9416]

sir ur videos r understanding vry clearly amazing

[@mben708]

Thank you. That was really helpful

[@akshayudupa6105]

19:48 - 1/50M is not 50micro sec

[@EDUVANCE]

It should be 0.02 micro seconds. Apologies for the inconvenience.

[@akshayudupa6105]

Your videos are very understandable. Thank you!

[@bryanchambers1964]

I am taking this class at TUM Munich and 3 weeks in what we are doing is more advanced than this vid, not bragging, but I am really struggling in my class.

[@pritam4622]

hi Dr. Jonathan Joshi, can we use any flipflop direct from library in vhdl while we designing mod-3 counters...
like we pic up filpflops as component in schematic design...

[@EDUVANCE]

Yes you can do that.
Following is the link to the guide for Flip - Flop component selection :
www.xilinx.com/support/documentation/sw_manuals/help/iseguide/mergedProjects/destech/html/cs_flip_flops_component_selection_guide.htm
Taking example of Asynchronous D- Flip flop. To directly use D - flip flop you can refer the following link which shows the input and output port names to be used.
www1.pldworld.com/@xilinx/html/technote/tool/manual/15i_doc/alliance/lib/lib5_9.htm
So now while you are creating the instances you will declare them with same names.
Example:
XLXI_20 : FDC
port map (C=>CLK,
CLR=>CLR,
D=>XLXN_44,
Q=>A_DUMMY);

[@pritam4622]

Thanks alot Dr. Joshi

[@shreyasbelose1230]

Sir,how to use for loop in vhdl ?? Will you please explain with an example

[@EDUVANCE]

The code below is an example of how to use for loop in VHDL.
In this code, If the input is 1, then it is inverted or else the output is same as input
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity MainModule is
Port ( invert : in std_logic;
input : in STD_LOGIC_VECTOR (3 downto 0);
output : out STD_LOGIC_VECTOR (3 downto 0));
end MainModule;
architecture Behavioral of MainModule is
begin
process(invert,input)
begin
if (invert='1') then
for I in 0 to 3
loop
output(I)

[@sagarwaghmare9416]

sir plz explain16×2 lcd dispaly vhdl coding