VHDL Lecture 17 Building Big Designs from Small Designs

Welcome to Eduvance Social.
Our channel has lecture series to make the process of getting started with technologies easy and fun so you can make interesting projects and products.
The channel hosts series of lectures to get started with different technologies covering topics like Programmable system on chip (PSoC), ARM mbed, Arduino, FPGA design using VHDL, VLSI design using Electric, Spice modelling using LT spice, PCB designing using Eagle, Robotics and much more to come.
Do like and subscribe to our channel.
Keep learning! Keep Eduvancing!

[@CallmeKaram]

I am truly enjoying the experience ♥ VhDL was never this easy

[@ntesla66]

Exactly what I needed. I'd been lost in a design that used built in IP (Quartus megawizard) and component instantiation. I decided to start at the beginning of your lectures and followed them all the way through to here (less the labs). I was able to get my design to compile after fixing the errors I'd made. Your videos helped me spot the errors and most certainly increased my proficiency over all in VHDL. I can not thank you enough.

[@movietalkies7310]

really helpful lectures ............THANKS FOR THE HELP

[@modulate72]

Thank you for your clear, excellent explanations.

[@coolwinder]

17:55 Can I write HA2: Lab6_2_halfadder portmap( A=>sum, B=>C, sum=>sum, carry=>carry2);
The sum=>sum is my question. Thanks, great videos!

[@EDUVANCE]

Yes that can be done.