VHDL Lecture 17 Building Big Designs from Small Designs
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- เผยแพร่เมื่อ 28 ส.ค. 2024
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I am truly enjoying the experience ♥ VhDL was never this easy
Exactly what I needed. I'd been lost in a design that used built in IP (Quartus megawizard) and component instantiation. I decided to start at the beginning of your lectures and followed them all the way through to here (less the labs). I was able to get my design to compile after fixing the errors I'd made. Your videos helped me spot the errors and most certainly increased my proficiency over all in VHDL. I can not thank you enough.
really helpful lectures ............THANKS FOR THE HELP
Thank you for your clear, excellent explanations.
17:55 Can I write HA2: Lab6_2_halfadder portmap( A=>sum, B=>C, sum=>sum, carry=>carry2);
The sum=>sum is my question. Thanks, great videos!
Yes that can be done.