All video is nice and easy to understand thanks for these all videos on VHDL I face issue all VHDL video are in random sequence. so I just want you to make the playlist so we can easily assess all video in a sequence manner.
i could not clearly understand why using elsif for clocked processed would generate a wrong hardware....could you please make a vedeo elaborating that topic and some other related coding styles which shall generate similar errors
While designing sequential circuits, you want your hardware to operate on clock edge for e.g. rising edge. So unless there is a signal which is asynchronous to your clock , say reset, you can declare the clock event in if block and end it with end if. Now in designs where we use if else structure, a priority logic is developed. The statements in if else structure are in decreasing order of priority starting from if to the last else statement. if (...){ will be checked first } else if (...){ will be checked only if 'if' statement is false } . . else{ will be checked only if 'if' and all 'else if' statements are false } Also asynchronous signals need to be given a higher priority than other signals in system which are synchronous since they can occur at any instant in the system. They are independently executed events which do not rely on rising or falling edge of clock. So while designing sequential circuits using if else which involves a asynchronous signal , all the asynchronous signals should be declared in descending order of their priority and in the last else if structure, your clock event should be declared. Now if you write a else or a else if block after your clock event,you will be assigning the signals or processes declared in that block a lesser priority than clock event which is a wrong design.
im trying to code a non restoring division and i have 2 if else statements in one process but they run concurrently when it should be sequential, how do i fix that? i tried nested loop but apparently it gives same result
Yes If its combinational circuits you are designing, it will depend on the input, output or control signals you put in the list. If you are designing a sequential circuit, it will depend on the value of clock, reset or any other asynchronous signal in the design.
The best source to learn VHDL on youtube.
Definitely appreciate your work putting together these excellent videos.
This is how to use slides to explain concepts. Amazing sir. My teachers need to learn this skills.
34:31 hahahaha this made me laugh
all the way you are awesome sir..
Greaaaaaat explanation and wonderful way to teach this subject, Keep going !
Very informative lecture, thank you so much!
All video is nice and easy to understand
thanks for these all videos on VHDL
I face issue all VHDL video are in random sequence.
so I just want you to make the playlist so we can easily assess all video in a sequence manner.
+Technocrat
Here is the link for the playlist of VHDL lecture videos th-cam.com/video/BDq8-QDXmek/w-d-xo.html
Eduvance Social
Thanks🙂
Please upload lecture 5 and all other further lectures this is really helpful.Thank you
Thanks a lot !!! Great explanation. Really!
your videos are awwsome....can u make a video on flipflop and laatches?
Yes. We are working on it.
thanks a lot for your very clear explanations
Very helpful tutorials. Bdw which software do you use to make the slides and the video?
We use Camtasia recorder. The writing software is windows journal.
Thank u sir
i could not clearly understand why using elsif for clocked processed would generate a wrong hardware....could you please make a vedeo elaborating that topic and some other related coding styles which shall generate similar errors
While designing sequential circuits, you want your hardware to operate on clock edge for e.g. rising edge. So unless there is a signal which is asynchronous to your clock , say reset, you can declare the clock event in if block and end it with end if.
Now in designs where we use if else structure, a priority logic is developed. The statements in if else structure are in decreasing order of priority starting from if to the last else statement.
if (...){ will be checked first
}
else if (...){ will be checked only if 'if' statement is false
}
.
.
else{ will be checked only if 'if' and all 'else if' statements are false
}
Also asynchronous signals need to be given a higher priority than other signals in system which are synchronous since they can occur at any instant in the system. They are independently executed events which do not rely on rising or falling edge of clock.
So while designing sequential circuits using if else which involves a asynchronous signal , all the asynchronous signals should be declared in descending order of their priority and in the last else if structure, your clock event should be declared.
Now if you write a else or a else if block after your clock event,you will be assigning the signals or processes declared in that block a lesser priority than clock event which is a wrong design.
concepts are clearer... Can u please load the other lecture 5 and so on.... thank u
Thank you. We are uploading more videos soon.
+SURAJ GAONKAR New lectures from lecture 5 onwards have been added for VHDL. Do check them out on out channel.
There is no more tutorials ? It was very informative by the way.
+abdelrahman tarief New lectures have been added for VHDL. Do check them out on out channel.
make more videos man
Thanks. We are uploading more soon
very clear
im trying to code a non restoring division and i have 2 if else statements in one process but they run concurrently when it should be sequential, how do i fix that? i tried nested loop but apparently it gives same result
Will the process code always be triggered when there is a change in the variables present in the sensitive list?????
Yes
If its combinational circuits you are designing, it will depend on the input, output or control signals you put in the list. If you are designing a sequential circuit, it will depend on the value of clock, reset or any other asynchronous signal in the design.
aage k lectures kaha h
+gurpeet singh New lectures have been added for VHDL. Do check them out on out channel.
+gurpeet singh New lectures have been added for VHDL. Do check them out on out channel.