VHDL Lecture 1 VHDL Basics
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- เผยแพร่เมื่อ 10 ก.ค. 2024
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very clear explanation but a bit slow. watch at 1.5x
You are the reason why I can't drop out of E.Engineering
I love all your Videos. Greetings from Germany
I have a minimal understanding of any coding, but I finished this video feeling like I really understood. Thank you so much!
super clarity of voice and concept, what a deep intensity of knowledge simply the best!!!!!!!
Great explanation, just reviewing my vhdl. Thank you.
better style of explanation. Thanks a lot :)
Awesome explanation! Thanks for your work.
Thanks for your lecture sir, very help me to understand VHDL languange.
thank you very very very very very very verey much!!!!! Great course!!!!!!!!!!! Greetings from Italy
Great! Thank you very much, this was brilliant!
excellent lecture
made a tough topic so easy and precise to understand
thanks a lot
Thank you sir
Easily explained lecture
Really appreciate ur work.. thank you so much sir.. looking forward for more lectures from you..
+Amit Pachpande New lectures have been added for VHDL. Do check them out on out channel.
Nice way of explaining. Appreciate it !
Much appreciated for your lecture 1
Thanks very much for this wonderful lecture
absolutely grt video..i cleared my all doubts
really well thought out explanation thank you so much
Helped me a lot. Greetings from Germany.
Thank you for your video it was very enlightening and greetings from Brazil.
excellent video...Thanks sir...
Best videos ever...i support you guys, please more videos!!!!!!!!!
great lecture .... but plz note that there is a couple of errors in it like in min 26:08 the A2: AND2 is incorrect it's AND1 not AND2 ..... also during your explanations in that time your cross mixed the information about the inputs and outputs between xor and the AND ..... but great job non the less
Yes. There is error inside begin. Following should be the statement :
A1 : AND1 port map (A, B, CARRY); (It should be AND1 instead of AND2)
Also here, A will be mapped to X, B to Y and CARRY to Z
Similarly for X1 : XOR1 port map (A, B, SUM);
A will be mapped to P, B will be mapped to Q and SUM to R.
Apologies for the inconvenience.
great videos thanx
Fantastic lecture, much thanks
good introduction. thanks a lot
Thanks. Your videos have been of great help to me.
Great video, helped me alot with this topic
Wonderful.
excellent teaching sir.supperb clarity
i like your all lecture. all topic are precise clearly
excellent video!, you're explanation is very clear :)
you have just showed what teaching style have we lost in our institutes
thank you sir for elegant videos
Thank you very much Sir for your helpful video.
Greeting from Iraq.
Thank u very much Sir...........We expect more videos on new topics..............!!
Excellent Video.
thank you so much ,that was very usefull and clearly
nice work there...........
I'm studying computer engineering, this language and its logic is not so hard to understand when one has the background of C and C++ programming
+John Cornner
Hi John
Just a thought with respect to HDL and c . The objective of an HDL is to design hardware. It is always good to think of the hardware you want to design and how an HDL can help you do so.
Thinking of an HDL from the perspective of a programming language might give some issues when it comes to simulation and the resultant hardware synthesized.
Cheers
Good work.. Keep it up 😃
Thank you sir!
ThanQ great work
Very helpful video sir.
excellent explanation...
thks man u made it easy thks.
thx.. this is really helpful for me :)
Thank you Rakesh
thank u so much...it is very easy to understand
thank u so much.......u explained very nicely!!!
Thankyou so much!
Thank you Sir...
excellent video
thank you very much sir
Thanks alot.
very well explained
the best tutorial
Really a great lecture.... Sir give me tha link of that video in which application of VHDL language are described 😊😊😊😊😊😊
super sir.. I want gate level modeling
Thank you. :)
thank u sir...
good lecture
Masha Allah great work sir.. you made it very easy to understand.. have you made lectures regarding to C# visual studio?
awesome
Nice video but I recommend u to watch in 1.5x speed
The explanation is very good, however, I struggle a little with some words that he was writing, and I would have liked that he would use a print screen with the rest of the examples just as he did with the first one, still a really good video thanks
Thank you for the feedback.
We will definitely work on it.
which simulator had u used in labs
Please upload new videos
set playback speed to ×1.25 save time
so if i want to learn VHDL in detail, is this series of videos appropriate?
+Prashant Saxena yes
can i get a vhdl code to display the position of 1's for 8 bit number
Making sure I understand this... the half-adder structural style created XOR and AND blocks but didn't yet assign a function or actual behavior. Is this correct?
Yes to implement the half adder using the structural style of modelling we first created XOR and AND components.
Then, to implement the half adder we used these components by using the keyword port map. The input and output of these components are mapped to those of half adder.
hello sir. which software would you suggest to do VHDL simulation practice for beginners
You can use Xilinx ISE Webpack 14.7
where to code in VHDL? Is there any software/editor for ubuntu? What is the final output of the code?
Yes. You can install Xilinx ISE to code in VHDL.
You implement a half adder successfully.
Whats the difference between behavioral and structural circuit
Taking the example of half adder as stated in the video. The structural implementation of Half Adder circuit was made using smaller components, which were And gate and Exor gate. Then we did port mapping of inputs and outputs to the respective components and designed it to function as a half adder.
For implementing half adder using behavioral implementation, you will describe the behavior of your circuit. It means you state that when A = 0 and B = 0 your Sum output should be 0 and Carry should be 0 , when A = 0 and B = 1 your Sum output should be 1 and Carry should be 0 and so on. You can use if-else structure, case structure or with select structure to create such designs.
You can refer following video link that explains behavioral and structural Implementation - th-cam.com/video/xYo92g3gEoI/w-d-xo.html
Thank you for giving me a brief introduction of vhdl entity and architecture >> concepts
howto comment a block of code in vhdl.................any suggestion will be appreciated
Step 1 : Select the block of code you want to comment.
Step 2 : Right click and go to comments, click on selection, the code will be commented.
thanks for that help