This should be a template for all instructional videos that try to address complex tools like Vivado and Vitis. Xilinx has a lot to learn when it comes to making videos explaining their tools to beginners, IMO. Thank you very much.
Thank you so much for this tutorial, I've been completely clueless on how am I supposed to work with it and had no idea where to start. This tutorial was an incredible starting point and I'm very grateful I stumbled upon it.
Thanks a lot for this video! I wanted to add a hint for newbies who may be struggling like I did: make sure your MiniZed boot mode is set to 'J' instead of 'F'!
It is very helpful. Are you able to put together a video to show us how to utilize the GigiEnthernet on the board the Zynq board and use the Ethernet board to transmit data to another computer? Thank you for your time!
When it comes to actual hardware, how does C interact with the "hardware"? When I build something using vivado, where can I output/input 1/0 using C/Vitis?
I’m using a Cora Z7 board and when I run the auto router in the block diagram it throws an error that the clk input is not connected to a valid source. The block diagram didn’t change the way yours did. Any idea what it could be?
Does Vitis HLS v2022.1 support built-in HLS Functions such as hls::Threshold, hls::Erode, hls::Dilate, hls::Mul, hls::Duplicate, hls::MinMaxLoc, hls::CvtColor etc. ?
I have a question re: minute 20:00. You have got your board plugged in... How is it plugged on? How is the Hello World app downloaded to the board? Over USB/UART? Over Ethernet, where the so called agent on the remote board grabs the files sent and places them in a specific location and runs the app? Over JTAG interface? Cheers
I want to print hello world on third party simulator Xcelium which is available in vivado.. can you please tell me how to do that? Or can you provide me with any tutorial to do so?
When attempting to Validate the Design, I keep getting the error ' [BD 41-758] The following clock pins are not connected to a valid clock source: /processing_system7_0/M_AXI_GP0_ACLK'. Any ideas?
In case anyone was wondering, if you have an 'M_AXI_GP0_ACLK' input pin, you need to connect that to the 'FCLK_CLK0' and that solves all your problems.
@@xEcko6 Thank you very much for your comment, it was very useful. Could you tell me the reason for this? Furthermore, I would be very happy if you have references to learn more about the platform. Thanks
Hello and thanks you for your videos on this channel. I'd like to learn the xilinx vitis software platform for programming software part and implementing the hardware part with it. Can you suggest me how to learn it and where should I start (like which user guides and ...).? Best regards
I'd suggest getting a demo board, like the Avnet minized. I think its only around $100 USD, then just do what you are already doing watch the videos and start creating your own projects. I have to say that watching the video is helpful, but doing it yourself will make what you learn stick.
@@isidroy , Did you manage to solve your problem? One question, did you use USB for debugging and another cable for USB-UART for UART communication on the terminal?
hello, thank you for the tutorial! i keep having a problem when trying to create the hello world application. when i select the "Hello World" example, i get the following message: "This application requires a Uart IP in the hardware." i am using zybo 7z010 board. what am i doing wrong? should i add at the beginning a UART ip core in vivado block diagram or something like that?
Great Tutorial. I Have some questions as I have recently purchased a KV260 board and am trying to port my code onto it. Do you have a discord where I can hit you up?
@15:08 you Browsed your project folder for your design_1_wrapper.xsa file and it successfully opened with Operating System: standalone and Processor: ps7_cortexa9_0. Well, when I selected my design_1_wrapper.xsa file it took a while BUT both the Operating System and Processor were greyed out and blank. It would not let me continue. So, can I select a default XSA and which one? Or do I need to go back and fix something? Note: since my free Vivado 2021.2 ML Version failed with the MiniZed board I had to substitute the Zybo Z7-20 (xc7z020clg400-1) board, Report IP status, Upgrade Selected, Generate the Output products which worked, Run Synthesis, Implementation, and Generate Bitstream successfully, Export the Bitstream file to Target HW, selected Zybo Z7-20's XSA file created in my project folder, Exported HW Platform. Then I opened Vitis Tools > Launch Vitis IDE > Create New Platform > hello_world_platform > XSA File: design_1_wrapper.xsa > Open > Reading HW specification. Software specification: Operating System: greyed out Processor: greyed out Aby suggestions on how to remedy this problem? After further investigation, it appears you skipped a few steps in Synthesis because you did not use a MiniZed board Constraints file and did not set the I/O pins for this design application. So, go the following critical warnings: General Messages [Common 17-55] 'set_property' expects at least one object. ["c:/Users/..../Documents/Xilinx/FPGA/Projects/RobertSwan/Hello_world_microzed/Hello_world_microzed.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0.xdc":33] [Vivado 12-1411] Cannot set LOC property of ports, Could not legally place instance design_1_i/processing_system7_0/inst/genblk13[31].MIO_BIBUF at E16 (IOPAD_X1Y108) since it belongs to a shape containing instance design_1_i/processing_system7_0/inst/PS7_i. The shape requires relative placement between design_1_i/processing_system7_0/inst/genblk13[31].MIO_BIBUF and design_1_i/processing_system7_0/inst/PS7_i that can not be honoured because it would result in an invalid location for design_1_i/processing_system7_0/inst/PS7_i. ["c:/Users/.../Documents/Xilinx/FPGA/Projects/RobertSwan/Hello_world_microzed/Hello_world_microzed.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0.xdc":188] Design Initialization [Common 17-55] 'set_property' expects at least one object. ["c:/Users/.../Documents/Xilinx/FPGA/Projects/RobertSwan/Hello_world_microzed/Hello_world_microzed.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0.xdc":33] [Vivado 12-1411] Cannot set LOC property of ports, Could not legally place instance design_1_i/processing_system7_0/inst/genblk13[31].MIO_BIBUF at E16 (IOPAD_X1Y108) since it belongs to a shape containing instance design_1_i/processing_system7_0/inst/PS7_i. The shape requires relative placement between design_1_i/processing_system7_0/inst/genblk13[31].MIO_BIBUF and design_1_i/processing_system7_0/inst/PS7_i that can not be honoured because it would result in an invalid location for design_1_i/processing_system7_0/inst/PS7_i. ["c:/Users/.../Documents/Xilinx/FPGA/Projects/RobertSwan/Hello_world_microzed/Hello_world_microzed.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0.xdc":188] So, do you have a recommended I/O Ports for the following this applications (86) signals? Thanks, JT
This should be a template for all instructional videos that try to address complex tools like Vivado and Vitis. Xilinx has a lot to learn when it comes to making videos explaining their tools to beginners, IMO. Thank you very much.
hello can u help me something with vitis
First tutorial so far that I could follow all the way through and everything works. Thanks for the video!
Thank you so much for this tutorial, I've been completely clueless on how am I supposed to work with it and had no idea where to start. This tutorial was an incredible starting point and I'm very grateful I stumbled upon it.
Thank you so much for this! I've had a look through at least 5 different tutorials until I saw yours and finally made my board do something!
Thanks a lot for this video! I wanted to add a hint for newbies who may be struggling like I did: make sure your MiniZed boot mode is set to 'J' instead of 'F'!
Thank you very much for the video! It's very helpful.
I wish I could upvote your video more than once
This is just the video I need to figure out simply how vivado and vitis cooperate. Thank you very much.
Thanks so much for making this!!! I'm a complete n00b, but you got me started.
quick and very informative, thanks mate
Great informative video for beginners.....
Robert great video tutorial, thanks. :)
Thanks for this video. Very helpful
Thankyou very much, this video was extremely helpful.
Excellent!
Very helpful. Thank you.
Thank you so much!
Thanks
It is very helpful. Are you able to put together a video to show us how to utilize the GigiEnthernet on the board the Zynq board and use the Ethernet board to transmit data to another computer?
Thank you for your time!
When it comes to actual hardware, how does C interact with the "hardware"? When I build something using vivado, where can I output/input 1/0 using C/Vitis?
I’m using a Cora Z7 board and when I run the auto router in the block diagram it throws an error that the clk input is not connected to a valid source. The block diagram didn’t change the way yours did. Any idea what it could be?
Thanks for your video, very usefull! Do you know the reason for Xilinx to switch SDK yo Vitis? It seems pritty much the same thing...
Hi. can I ask where did the M_AXI_GPO_ACLK go??
Does Vitis HLS v2022.1 support built-in HLS Functions such as hls::Threshold, hls::Erode, hls::Dilate, hls::Mul, hls::Duplicate, hls::MinMaxLoc, hls::CvtColor etc. ?
Much Appreciated!! Helped me with Udemy Course 'Learn Fundamentals of FPGA and VHDL Development; Lecture 70
Is it work with picorv32 with some interconnect and peripherals ?
And if I don't want to use an IP? To just write VHDL and synthesize that (after providing a target chip of course)?
why are there 2 board support packages in the video?
good video, but it doesn't tell about licensing - I changed the chip to Kintex UltraScale XCKU15P and it says I don't have license for HLS synthesis
I have a question re: minute 20:00. You have got your board plugged in... How is it plugged on? How is the Hello World app downloaded to the board? Over USB/UART? Over Ethernet, where the so called agent on the remote board grabs the files sent and places them in a specific location and runs the app? Over JTAG interface? Cheers
Hello, thanks for the video. Can you explain what are the differences between Xilinx SDK and Vitis ?
SDK is derived from xilinx vivado & vitis is followed from vivado 2019 .
I want to print hello world on third party simulator Xcelium which is available in vivado.. can you please tell me how to do that? Or can you provide me with any tutorial to do so?
is there a tutorial to do this for linux platform, i keep getting a sd card error
When attempting to Validate the Design, I keep getting the error ' [BD 41-758] The following clock pins are not connected to a valid clock source:
/processing_system7_0/M_AXI_GP0_ACLK'.
Any ideas?
In case anyone was wondering, if you have an 'M_AXI_GP0_ACLK' input pin, you need to connect that to the 'FCLK_CLK0' and that solves all your problems.
@@xEcko6 Thank you very much for your comment, it was very useful. Could you tell me the reason for this? Furthermore, I would be very happy if you have references to learn more about the platform. Thanks
You should have included a GPIO component in the tutorial so it would be even better!
I want to recive gps data through uart on zed board. how to do that?
Hello and thanks you for your videos on this channel.
I'd like to learn the xilinx vitis software platform for programming software part and implementing the hardware part with it.
Can you suggest me how to learn it and where should I start (like which user guides and ...).?
Best regards
I'd suggest getting a demo board, like the Avnet minized. I think its only around $100 USD, then just do what you are already doing watch the videos and start creating your own projects. I have to say that watching the video is helpful, but doing it yourself will make what you learn stick.
@@robertswan8546 Thank you very much
Hello sir,thanks for the video,how to work with lwip tcp server client application vitis in qemu emulator?if possible please tell us the procedure.
Unable to create firmware project...
While connection to com4 is successful at this baud rate, the terminal prints nothing. Is there any suggestion?
I had the same problem.. I closed Vitis, connected the board and open Vitis again. It worked for me.
@@isidroy , Did you manage to solve your problem? One question, did you use USB for debugging and another cable for USB-UART for UART communication on the terminal?
hello, thank you for the tutorial! i keep having a problem when trying to create the hello world application. when i select the "Hello World" example, i get the following message: "This application requires a Uart IP in the hardware." i am using zybo 7z010 board. what am i doing wrong? should i add at the beginning a UART ip core in vivado block diagram or something like that?
Were you able to program the board? What version of Vivado were you using?
@Kiernan King 2019.2 i come back tomorrow with the details.
You keep referring to IP. Internet Protocol? Intellectual Property?
Intellectual property
I am using Vivado 2020.02. But there are no Zynq when I want to Add IP. Who know why?
Maybe you missed something in the installation process. I installed it two-three days ago and it works perfectly fine.
Great Tutorial. I Have some questions as I have recently purchased a KV260 board and am trying to port my code onto it. Do you have a discord where I can hit you up?
@15:08 you Browsed your project folder for your design_1_wrapper.xsa file and it successfully opened with Operating System: standalone and Processor: ps7_cortexa9_0.
Well, when I selected my design_1_wrapper.xsa file it took a while BUT both the Operating System and Processor were greyed out and blank.
It would not let me continue. So, can I select a default XSA and which one?
Or do I need to go back and fix something?
Note: since my free Vivado 2021.2 ML Version failed with the MiniZed board I had to substitute the Zybo Z7-20 (xc7z020clg400-1) board, Report IP status, Upgrade Selected, Generate the Output products which worked, Run Synthesis, Implementation, and Generate Bitstream successfully, Export the Bitstream file to Target HW, selected Zybo Z7-20's XSA file created in my project folder, Exported HW Platform.
Then I opened Vitis Tools > Launch Vitis IDE > Create New Platform > hello_world_platform > XSA File: design_1_wrapper.xsa > Open > Reading HW specification.
Software specification:
Operating System: greyed out
Processor: greyed out
Aby suggestions on how to remedy this problem?
After further investigation, it appears you skipped a few steps in Synthesis because you did not use a MiniZed board Constraints file and did not set the I/O pins for this design application. So, go the following critical warnings:
General Messages
[Common 17-55] 'set_property' expects at least one object. ["c:/Users/..../Documents/Xilinx/FPGA/Projects/RobertSwan/Hello_world_microzed/Hello_world_microzed.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0.xdc":33]
[Vivado 12-1411] Cannot set LOC property of ports, Could not legally place instance design_1_i/processing_system7_0/inst/genblk13[31].MIO_BIBUF at E16 (IOPAD_X1Y108) since it belongs to a shape containing instance design_1_i/processing_system7_0/inst/PS7_i. The shape requires relative placement between design_1_i/processing_system7_0/inst/genblk13[31].MIO_BIBUF and design_1_i/processing_system7_0/inst/PS7_i that can not be honoured because it would result in an invalid location for design_1_i/processing_system7_0/inst/PS7_i. ["c:/Users/.../Documents/Xilinx/FPGA/Projects/RobertSwan/Hello_world_microzed/Hello_world_microzed.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0.xdc":188]
Design Initialization
[Common 17-55] 'set_property' expects at least one object. ["c:/Users/.../Documents/Xilinx/FPGA/Projects/RobertSwan/Hello_world_microzed/Hello_world_microzed.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0.xdc":33]
[Vivado 12-1411] Cannot set LOC property of ports, Could not legally place instance design_1_i/processing_system7_0/inst/genblk13[31].MIO_BIBUF at E16 (IOPAD_X1Y108) since it belongs to a shape containing instance design_1_i/processing_system7_0/inst/PS7_i. The shape requires relative placement between design_1_i/processing_system7_0/inst/genblk13[31].MIO_BIBUF and design_1_i/processing_system7_0/inst/PS7_i that can not be honoured because it would result in an invalid location for design_1_i/processing_system7_0/inst/PS7_i. ["c:/Users/.../Documents/Xilinx/FPGA/Projects/RobertSwan/Hello_world_microzed/Hello_world_microzed.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0.xdc":188]
So, do you have a recommended I/O Ports for the following this applications (86) signals?
Thanks,
JT