That was an excellent explanation - thank you! I have followed some other similar tutorials but, at the end, nothing appeared in the terminal. You explained *why* some things are the way they are and that helped me figure out how to get the example to work with my particular board. I'm also grateful that you did this with SDK and not Vitis. I tried Vitis and got nowhere quickly. I ended up downgrading Vivado to an earlier version so that I could use SDK.
This is a neat concise explanation. Great. For me, at the end of bit stream generation, I get the follwoing warning. Is it safe to ignore and donwload to the board? Or should I add a .xdc with only the 2 entries for CFGBVS and CONFIG_VOLTAGE at the wrapper? Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0 ....
@@abhaydeshmukh2642 it worked straight away on AC701 evaluation board without any change in the XDC file. I am not sure if you are using any custom board
@@letslearn39 Frist of all, thanks for taking the time out and responding. I am also using ac701. I just wanted to know if I am doing something wrong, since I got those warnings. If you also had got the warning and still the program has worked, then it is great and I will also do the same.
Thank you for the video. I have THREE questions. 1. Can Xilinx SDK accept MicroBaleze's ASM program? 2. If not, how to make ASM work? 3. If I have my own processor core (like a variant of RISC-V, I will create and add IP in the Vivao. and export the bit file to SDK). Now: how does SDK understand RISC-V C/ASM language? If possible can you make a video on RISC-V porting onto FPGA? Thanks.
First of all, thumbs up for an excellent tutorial. I have a question... While implementing we need to specify the .xdc for the project. Perhaps I skipped that part in your video, or is it simply missing?
if you are using a board which is supported by vivado, then while doing connection automation after adding a resource, the pins will be automatically assigned. You need not manually make any entry in the XDC file. If you are using a custom board, then for all the external IO pins you need to specify the pin number and IO standard in the XDC file. This demo used AC701 board from Xilinx, hence the manual creation of XDC was not required.
@@MuhammadQasimRauf Nexys is a board from Digilent. So you need install the board files once after installing vivado. If you have done that, then at the start of the project at the part selection stage, you will be able to select the Nexys from the 'boards' tab. Once you do that connection automation will take care of everything.
@@letslearn39 Yes I have done that and the board is up and running with simple Verilog codes like UART. A useful information for someone trying to run SDK with Vivado 2019! When you save your project then the root directory ought not include any space, else Vivado won't allow you to open SDK. I have noticed you saved your project by default in a directory that didn't create trouble for you.
Thank you for such a detailed explanation. Could you please tell me how many UARTs can we implement using this MicroBlaze processor in an Artix 7 FPGA? Can we implement 15 UARTs? And what can be the maximum baud rate? Can it be 460800?
Does Vitis HLS v2022.1 support built-in HLS Functions such as hls::Threshold, hls::Erode, hls::Dilate, hls::Mul, hls::Duplicate, hls::MinMaxLoc, hls::CvtColor etc. ?
I am building using Vivado 2018.3 and I have created the microblaze+uart wrapper. However, I get an error when I generate the bitstream. I thought it was because I had the basys3 board as the target. I stepped back and used only the Artix7 chip as the target with no other IO constraints. It completes implementation but fails generating the bit stream. This is the error I get: [DRC NSTD-1] Unspecified I/O Standard: 18 out of 18 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: uart_rtl_0_baudoutn, uart_rtl_0_ctsn, uart_rtl_0_dcdn, uart_rtl_0_ddis, uart_rtl_0_dsrn, uart_rtl_0_dtrn, uart_rtl_0_out1n, uart_rtl_0_out2n, uart_rtl_0_ri, uart_rtl_0_rtsn, uart_rtl_0_rxd, uart_rtl_0_rxrdyn, uart_rtl_0_txd, uart_rtl_0_txrdyn, reset_rtl_0_0... and (the first 15 of 18 listed). Can someone explain to me what the issue is? -- Thanks,
Instead of clicking on "Generate Bitstream" from the beginning, you should click "Run Synthesis". After it has completed, change the perspective from the drop down in the top-right corner of Vivado to "I/O Planning". Find out how to auto-assign all the pins except for the clock and the UART_RX_OUT pin (which depends on your specific board). I'm using the Arty 7 board and the clock pin should be E3 and UART_RX_OUT pin should be D10. After you save the I/O, an .xdc (constraint) file will be generated and you can then proceed with Implementation and generation of bitstream.
hi, sir I need your help in learning ethernet connection from FPGA board VCU108. it's very urgent, please help me in this how can I send a constant value to ethernet ip and exctract it on the terminal through ethernet. Please help me sir.
Hello sir can u please share ur gmail id . I am getting some error when I chose empty application i.e undefined reference to main . Can u please help me sort this error out
Its 2020 and you show the early 2019 deprecated SDK.... Vitis is the way you need to go these days. This tutorial should not be viewed by anyone really seeking help
If you are looking for same demo on Vitis, use the link below th-cam.com/video/Ns6yOsQ2jvk/w-d-xo.html As of now the user base is much higher for SDK than Vitis (except for acceleration and AI). Thank you for the feedback.
I m getting error when I opened sdk ........ 13:37:28 Error : unable to create hardware specification project with specification file : c:/users/admin/desktop/vivado
That was an excellent explanation - thank you! I have followed some other similar tutorials but, at the end, nothing appeared in the terminal. You explained *why* some things are the way they are and that helped me figure out how to get the example to work with my particular board. I'm also grateful that you did this with SDK and not Vitis. I tried Vitis and got nowhere quickly. I ended up downgrading Vivado to an earlier version so that I could use SDK.
Nice explanation. These kind of contents are much need. Thank you for putting in your time.
It was a fabulous explanation...!
clear explanisation 🔥
thanks a lot. super nice.
Such a simple yet detailed and neat demonstration. Can you show how to run DMA loopback test on MicroBlaze?
This is a neat concise explanation. Great. For me, at the end of bit stream generation, I get the follwoing warning. Is it safe to ignore and donwload to the board? Or should I add a .xdc with only the 2 entries for CFGBVS and CONFIG_VOLTAGE at the wrapper?
Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0 ....
@@abhaydeshmukh2642 it worked straight away on AC701 evaluation board without any change in the XDC file. I am not sure if you are using any custom board
@@letslearn39 Frist of all, thanks for taking the time out and responding.
I am also using ac701. I just wanted to know if I am doing something wrong, since I got those warnings. If you also had got the warning and still the program has worked, then it is great and I will also do the same.
Nice explanation
Thank you for the video. I have THREE questions. 1. Can Xilinx SDK accept MicroBaleze's ASM program? 2. If not, how to make ASM work? 3. If I have my own processor core (like a variant of RISC-V, I will create and add IP in the Vivao. and export the bit file to SDK). Now: how does SDK understand RISC-V C/ASM language? If possible can you make a video on RISC-V porting onto FPGA? Thanks.
Can u please provide a test bench code for the design
First of all, thumbs up for an excellent tutorial.
I have a question... While implementing we need to specify the .xdc for the project. Perhaps I skipped that part in your video, or is it simply missing?
if you are using a board which is supported by vivado, then while doing connection automation after adding a resource, the pins will be automatically assigned. You need not manually make any entry in the XDC file. If you are using a custom board, then for all the external IO pins you need to specify the pin number and IO standard in the XDC file. This demo used AC701 board from Xilinx, hence the manual creation of XDC was not required.
@@letslearn39 I'm assuming that same goes for my Nexys Video board? I needn't add any XDC?
@@MuhammadQasimRauf Nexys is a board from Digilent. So you need install the board files once after installing vivado. If you have done that, then at the start of the project at the part selection stage, you will be able to select the Nexys from the 'boards' tab. Once you do that connection automation will take care of everything.
@@letslearn39 Yes I have done that and the board is up and running with simple Verilog codes like UART.
A useful information for someone trying to run SDK with Vivado 2019! When you save your project then the root directory ought not include any space, else Vivado won't allow you to open SDK. I have noticed you saved your project by default in a directory that didn't create trouble for you.
@@MuhammadQasimRauf Many IDEs doesn't allow space in the path. So as a standard practice it's always better to avoid space in path name.
Thank you for such a detailed explanation. Could you please tell me how many UARTs can we implement using this MicroBlaze processor in an Artix 7 FPGA? Can we implement 15 UARTs? And what can be the maximum baud rate? Can it be 460800?
Does Vitis HLS v2022.1 support built-in HLS Functions such as hls::Threshold, hls::Erode, hls::Dilate, hls::Mul, hls::Duplicate, hls::MinMaxLoc, hls::CvtColor etc. ?
I have not worked with HLS
I am building using Vivado 2018.3 and I have created the microblaze+uart wrapper. However, I get an error when I generate the bitstream. I thought it was because I had the basys3 board as the target. I stepped back and used only the Artix7 chip as the target with no other IO constraints. It completes implementation but fails generating the bit stream. This is the error I get:
[DRC NSTD-1] Unspecified I/O Standard: 18 out of 18 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: uart_rtl_0_baudoutn, uart_rtl_0_ctsn, uart_rtl_0_dcdn, uart_rtl_0_ddis, uart_rtl_0_dsrn, uart_rtl_0_dtrn, uart_rtl_0_out1n, uart_rtl_0_out2n, uart_rtl_0_ri, uart_rtl_0_rtsn, uart_rtl_0_rxd, uart_rtl_0_rxrdyn, uart_rtl_0_txd, uart_rtl_0_txrdyn, reset_rtl_0_0... and (the first 15 of 18 listed).
Can someone explain to me what the issue is? -- Thanks,
I have the same problem. Did you fix it?
Instead of clicking on "Generate Bitstream" from the beginning, you should click "Run Synthesis". After it has completed, change the perspective from the drop down in the top-right corner of Vivado to "I/O Planning". Find out how to auto-assign all the pins except for the clock and the UART_RX_OUT pin (which depends on your specific board). I'm using the Arty 7 board and the clock pin should be E3 and UART_RX_OUT pin should be D10. After you save the I/O, an .xdc (constraint) file will be generated and you can then proceed with Implementation and generation of bitstream.
hi, sir
I need your help in learning ethernet connection from FPGA board VCU108.
it's very urgent, please help me in this how can I send a constant value to ethernet ip and exctract it on the terminal through ethernet. Please help me sir.
are you malayali?
Yes
@@letslearn39 can u help me with a doubt
Like si vienes por embebidos
Hello sir can u please share ur gmail id .
I am getting some error when I chose empty application i.e undefined reference to main .
Can u please help me sort this error out
letslearnembedded@gmail.com
Its 2020 and you show the early 2019 deprecated SDK.... Vitis is the way you need to go these days. This tutorial should not be viewed by anyone really seeking help
If you are looking for same demo on Vitis, use the link below
th-cam.com/video/Ns6yOsQ2jvk/w-d-xo.html
As of now the user base is much higher for SDK than Vitis (except for acceleration and AI). Thank you for the feedback.
That's not true at all. @Let's Learn good job.
Even if that were true, designs still have to be maintained and modified that were done through SDK. This isn't useless info.
I m getting error when I opened sdk ........
13:37:28 Error : unable to create hardware specification project with specification file : c:/users/admin/desktop/vivado
Please make sure that there are no space in path name of your project.