I spent probably an hour trying to find a video like this. Thank you so much for the all hard work that went into this. I’m really hoping you have more.
This video was great btw. Really well made, very informative, and super easy to follow. I've programmed FPGA's before but never with Vivado so this was a great way to introduce me to the way the program operates. Much appreciated.
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Hats off to you man. After watching about 20-30 videos on Xilinx I couldnt find a video that could get me started with basics. Your video just did that. I am on a journey to build a Neural Network using FPGA. You have helped me getting started. Thanks a ton. More videos from you on CNN using FPGA would be absolutely fantastic
Absolutely fantastic video! FPGAs seem to have an extremely steep learning curve, so the syntax distance between true newby and somebody with a few weeks experience is vast! Just a few minutes learning your way around Vivado and basically learning definitions is a huge boost that your video did an exceptional job with. Thanks so much and looking forward to future videos. I know well done videos take a ridiculous amount of time to produce, and you look like a very busy guy...but here's hoping nonetheless!
@Joe Plocki I hope you were at least able to climb that initial barrier to entry and get on your way! I always found it frustrating that most online tutorials never bother to explain the fundamentals, hiding behind the excuse that "it's obvious". In my experience, it's often a lack of fundamental understanding. Good luck with your FPGA journey!
Excellent video. I just got a BASYS3 board and this is the clearest basic explanation of the Vivado software I’ve found I learned a lot that was missing from the other videos I watched. This could be considered a gold standard. I know it isn’t easy, but I wish you’d make more videos on more complex Vivado designs or even general digital design. Thanks.
This is a great tutorial, and one that is hard to find. I'm not sure why there are so few resources about FPGA programming on TH-cam, specially when it comes to Xilinx FPGAs, but this is the sort of educational video that should blow up. Thanks very much for this, just subscribed, hoping to find more content in the future!
Thanks! This video is still helping people get up to speed on Vivado. Today is 8/14/2022, four years after this video was made. I'm using VHDL and USB104-A7 board and this video was still very helpful! Thanks again.
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Thank you!! I followed your video and got the implementation to work on my arty S7! The explanation of constraints was especially helpful and pointed me to what information I needed in order to set them up. One point to those working on linux..... read the vivado release notes....the option to install the cable drivers has been removed from the install. The cable drivers have to be installed after you install vivado by running a script...otherwise vivado will not be able to see the board and you will not be able to program it.
Overengineering simple things like this is THE ABSOULTE BEST way to teach someone something, and we owe you a lot for this tutorial! Thank you very much!
That's a sweet development kit. I hope I can add some more material in the coming months that might help you get the most out of the Zynq series FPGAs. Thanks!
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Oh dear here i am looking for Vivado FPGA info & your vid appears with a picture of Cathedral Cove on the Coromandel Penninsula, New Zealand... As a very young child in the 1960s my parents took my brother & myself there by boat (the only access then) for a summertime family picnic. The sea became very rough late afternoon & we all almost DROWNED attempting to row back out in the dingy through the surf to the boat.... a terrible childhood memory. I hope you video bodes well however...
really nice and cool tutorial not leave it out, go ahead to create your tutorial of FPGA for advanced level, because you have really nice instructive methods.
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I need a fpga therapist. Is someone here available? Why there is no more videos in this channel? the first one gives me the impression that this therapist is really good! :D
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Excellent video! Some suggestions: Rather than specify the exact FPGA model, package, etc., it’s easier to specify the Digilent board name, which will set the FPGA parameters automatically. Lastly, just a minor point-when calculating the current through the LED you forgot to account for the forward voltage drop of the LED, which for a green LED is ~2 volts. So the current is (3.3 - 2.0)/R.
Hi Jerry, thanks for your thoughtful comments! I originally intended to do as you suggest, but decided it would be more valuable to walk the students through the process so they could understand what those options mean. Certainly, in later classes, I have students create projects for pre-defined boards (which is much simpler!) Also, I realised shortly after uploading the video that I didn't take into account the forward voltage drop across the LEDs. Oops! Have a wonderful weekend and thanks again.
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Hey your name fpga therapy is great, I was a bit stressed with being stuck with my fpga and seeing this helped feel better. However I thought to finish projects you always need to combine them with Vitis (SDK before) and TeraTerm but now you just did it with only Vivado?!
Hi Silvercat4, I'm glad you felt at ease after watching this video. FPGAs are beautiful, but they do take time to understand. After that, it's great! If you want to program a MicroBlaze core or the processing subsystem (PS / CPU) on a system-on-chip FPGA (e.g., a Zynq) then Vitis is useful. As for TeraTerm, I think any terminal/emulator will work. If all you want to do is configure the programmable logic (PL / FPGA) then you just need Vivado. There's a lot that can be learned before bringing MicroBlaze or a PS into the mix! :)
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Thanks, Rob. I appreciate it! I plan to produce a few more videos using similar (entry-level) FPGA platforms. If there's a topic you'd like me to cover, please let me know.
@@fpgatherapy I am trying to port an application written in C++ to the VCU1525, maybe a tutorial on the workflow of converting a simple c++ program to a bitstream? Are you aware of any significant workflow differences that I should be aware of when working with the VCU?
@@robmartin7873 That's a very powerful development kit. There are considerable workflow differences between conventional 'software' development (e.g., C, C++) and FPGA development. I find that the more experienced you are at software, the more difficult it is to build the intuition for how your code is translated into a functioning program (or bitstream) on the FPGA. It's important to understand how the synthesis and implementation tools translate your code into basic logic elements. I've also found that a lot of students take some time to get used to the fact that everything is happening all the time on the FPGA, and not necessarily in a defined sequence. Ultimately, translating a software algorithm onto an FPGA often depends on a) the nature of the algorithm (e.g., signal processing vs. pure logic vs. a procedural, etc.); b) your specific goal (performance, functionality, parallelization, determinism), and c) how patient you are. When did you begin with the ZCU?
@@fpgatherapy We got our hands on the VCU back in the summer of 2018, we quickly discovered that we were in way over our heads, and hired an FPGA dev, he spent 3 months on the project and stated that he could not overcome some kind of library issue. So the project has been dormant for a few months, however it bothers me having such a powerful piece of equipment sitting idle. Do you offer consulting services by chance?
Hi, thank you for uploading this nice explanatory tutorial. Can you make a video of a design using differential clock of virtex - 7 board in constraint file. I have trouble in generating differential clock of the board and connect it with the design. Thanks
Hi Naveen. I had planned this out, actually, and have some code ready that may be of some help prior to me releasing a new video. Your FPGA will have positive and negative (differential) clock pins on it. In your constraints file, you need to specify the pin locations and IO standards according to your development board's datasheet. It might look something like this (for a ZCU104 Zynq UltraScale+ development board): set_property PACKAGE_PIN E23 [get_ports "CLK_125_N"]; # Bank 28 VCCO - VCC1V8 - IO_L13N_T2L_N1_GC_QBC_28 set_property IOSTANDARD LVDS [get_ports "CLK_125_N"]; # Bank 28 VCCO - VCC1V8 - IO_L13N_T2L_N1_GC_QBC_28 set_property PACKAGE_PIN F23 [get_ports "CLK_125_P"]; # Bank 28 VCCO - VCC1V8 - IO_L13P_T2L_N0_GC_QBC_28 set_property IOSTANDARD LVDS [get_ports "CLK_125_P"]; # Bank 28 VCCO - VCC1V8 - IO_L13P_T2L_N0_GC_QBC_28 You'll also want to specify that CLK_125_P is a clock (it will propagate this information for CLK_125_N). Do this with some code in the constraints file like this: create_clock -period 8.000 -name CLK_125_P [get_ports CLK_125_P] Note: '-period 8.000' specifies the clock's period in nanoseconds. The ZCU104's clocks have a frequency of 125 MHz, so the period is 8.000 ns. Place this create_clock command above the set_property commands in your constraints file. If you want to generate a single-ended clock based on your differential input clock, you should use an IBUFGDS (stands for input buffer, global differential signal) in your top-level VHDL or Verilog file. IBUFGDS #( .IOSTANDARD("LVDS") // Specify the input I/O standard ) IBUFGDS_inst ( .O(clk), // Buffer output .I(CLK_125_P), // Diff_p buffer input (connect directly to top-level port) .IB(CLK_125_N) // Diff_n buffer input (connect directly to top-level port) ); You could test this out in Verilog with the following code (in addition to the constraints file you'll need to create): module clockCreation_TOP( input CLK_125_N, input CLK_125_P ); wire clk;
IBUFGDS #( .IOSTANDARD("LVDS") // Specify the input I/O standard ) IBUFGDS_inst ( .O(clk), // Buffer output .I(CLK_125_P), // Diff_p buffer input (connect directly to top-level port) .IB(CLK_125_N) // Diff_n buffer input (connect directly to top-level port) );
// Example clocked process using the newly generated clock reg [31:0] counter;
Time 18:09: You said there are "anode connected resistors". Actually, they are cathode connected. Great tutorial. How can I activate all the leds on one of the 7-segments led display? Thanks a lot!
Hey Brother, firstly great Video. Why have the videos stopped? I have a ZC706, needed help with storing my verilog code in memory so when the power goes off it doesn't forget everything. Couldn't find any more of your videos.
@FPGA Therapy I am running a Zynq on the Zybo dev board. I would absolutely love to see you do a video fixing errors. I am currently having trouble fixing a "no such directory"/"could not read file error , yet the directory and file do you exist. This was while using Vivado IDE just before generating a bitstream. I think it has something to do with generating the design constraints and creating IOSTANDARD constraint ".../axis gpo 0/gpo io o[0]" not directly connected to top level port. Nevertheless a tutorial on the TLC console and output messages and solving errors we would be most appreciated. You do an excellent job explaining.
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I had this problem come up once ‘could not read file’, it seemed to be to do with Windows file path length - I was using Microsoft Onedrive at the time. The problem went away after I transferring the project directory to the local hard drive.
Unfortunately there are many reasons this could happen. Are you running Vivado on Linux or Windows? I'm sure by now you've solved this problem. Good luck in the future.
You can, but it's good to define the IO constraints manually in tcl. It also allowed me to demonstrate how to use the data sheet to answer the unknown questions about IO voltage standards etc.
Great video! Questions: Why didn't the output port appear in the verilog file? Also, I always end each constraint with a semi-colon, is this no longer required? Thanks!
Hi Curtis, I discovered soon after putting this video together that I failed to press 'enter' after typing in the name for the output port. As for terminating constraints / lines in Tcl, you can use a semicolon if that's your style, but it's not strictly necessary because a new line has the same effect. I have not tried multiple constraints on a single line separated by semicolons, but I imagine this would be valid as well. Thanks for your support and encouragement. Lyle
How do you get the speed grade when selecting the part? I've been looking through the box of the board, but I haven't found anything regarding the speed.
Hi AnMoMu, If you go to 2:54 on the video you'll see a close up of the FPGA chip. This close up picture shows the device family Artix-7, part number (XC7A100T) and package identifier (CSG324). The line below the package identifier is the 'Lot Code' (useful for traceability and verification of the part). Then, immediately below the Lot Code is a number (1) and letter (C). The number '1' indicates the device speed grade (in this case, the higher the number, the faster the FPGA's minimum performance in terms of clock speed... i.e., higher speed grade -> faster designs). The letter indicates the device's temperature grade (C = Commercial, I = Industrial, and E = Extended). The Nexys-4 DDR's Artix-7 has a speed grade 1 and temperature grade C. Note: it's unlikely you'll find a development board with a temperature grade other than C, but perhaps some boutique reference boards do. I hope this is helpful.
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Here is me thanking you in 2024 for making this video. I searched hours but couldn't find a better one than this. Thank you!!!
I spent probably an hour trying to find a video like this. Thank you so much for the all hard work that went into this. I’m really hoping you have more.
This video was great btw. Really well made, very informative, and super easy to follow. I've programmed FPGA's before but never with Vivado so this was a great way to introduce me to the way the program operates. Much appreciated.
You're welcome :) I'm very glad to hear this video was helpful!
Thank you, During my bachelor degree I didn’t have this much clarity. Felt happy after seeing this and getting completely clear.
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Hats off to you man. After watching about 20-30 videos on Xilinx I couldnt find a video that could get me started with basics. Your video just did that. I am on a journey to build a Neural Network using FPGA. You have helped me getting started. Thanks a ton. More videos from you on CNN using FPGA would be absolutely fantastic
Hey did u complete your project? I need some help.
Absolutely fantastic video! FPGAs seem to have an extremely steep learning curve, so the syntax distance between true newby and somebody with a few weeks experience is vast! Just a few minutes learning your way around Vivado and basically learning definitions is a huge boost that your video did an exceptional job with. Thanks so much and looking forward to future videos. I know well done videos take a ridiculous amount of time to produce, and you look like a very busy guy...but here's hoping nonetheless!
steep learning curve is an understatment
@Joe Plocki I hope you were at least able to climb that initial barrier to entry and get on your way! I always found it frustrating that most online tutorials never bother to explain the fundamentals, hiding behind the excuse that "it's obvious". In my experience, it's often a lack of fundamental understanding.
Good luck with your FPGA journey!
Thanks for your work, sir
Excellent video. I just got a BASYS3 board and this is the clearest basic explanation of the Vivado software I’ve found I learned a lot that was missing from the other videos I watched. This could be considered a gold standard. I know it isn’t easy, but I wish you’d make more videos on more complex Vivado designs or even general digital design. Thanks.
This is soooo good! You should keep making videos, you are very talented at explaining. Have a good day :)
Thank you. I will try to prepare some more videos in the next couple of months. Please let me know if you'd like me to cover anything in particular.
@@fpgatherapy using intern RAM oder static memory to store some random data. :)
@@fpgatherapy please make videos on how to make Logic gates, servo control and other simple projects like PWM. Waiting for your next video on FPGA
@@fpgatherapy When are you going to make more FPGA videos? We need you to make more, please. You"re one of a kind instructor! Kudos!
This is a great tutorial, and one that is hard to find. I'm not sure why there are so few resources about FPGA programming on TH-cam, specially when it comes to Xilinx FPGAs, but this is the sort of educational video that should blow up. Thanks very much for this, just subscribed, hoping to find more content in the future!
Thanks, Matheus. It requires quite a lot of effort to produce this kind of video. I appreciate your kind words!
Thanks! This video is still helping people get up to speed on Vivado. Today is 8/14/2022, four years after this video was made. I'm using VHDL and USB104-A7 board and this video was still very helpful! Thanks again.
Great expansion!! PLEASE keep the videos coming.
You should keep making videos, you are very talented at explaining
great ! my 1st FPGA verilog lesson building an over engineered light bulb was a huge success. thank you :)
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best video i've seen on vivado so far. keep it up!
Excellent work Sir. Lyle.!
Thank you!! I followed your video and got the implementation to work on my arty S7! The explanation of constraints was especially helpful and pointed me to what information I needed in order to set them up. One point to those working on linux..... read the vivado release notes....the option to install the cable drivers has been removed from the install. The cable drivers have to be installed after you install vivado by running a script...otherwise vivado will not be able to see the board and you will not be able to program it.
yes, I got stuck at this point for some time!
Wow, great video man! You provided so much detail and I learned so much. Thank you!
Overengineering simple things like this is THE ABSOULTE BEST way to teach someone something, and we owe you a lot for this tutorial! Thank you very much!
Excellent video for beginners. Thanks a lot!
Awesome! I was able to follow along and get it going with my ZC706. Thanks!
That's a sweet development kit. I hope I can add some more material in the coming months that might help you get the most out of the Zynq series FPGAs. Thanks!
you have very nice voice for this kind of tutorials, keep it up, very calm, very clear, very informative. i hope to see more videos from you.
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Very clear and understandable. Thank you!!!
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Awesome video. Thanks a lot!
Oh dear here i am looking for Vivado FPGA info & your vid appears with a picture of Cathedral Cove on the Coromandel Penninsula, New Zealand... As a very young child in the 1960s my parents took my brother & myself there by boat (the only access then) for a summertime family picnic. The sea became very rough late afternoon & we all almost DROWNED attempting to row back out in the dingy through the surf to the boat.... a terrible childhood memory. I hope you video bodes well however...
That's horrible! I'm glad everything worked out and you can now associate those memories with Xilinx development tools! :P
Just kidding.
You are an angel sent from above...
really nice and cool tutorial not leave it out, go ahead to create your tutorial of FPGA for advanced level,
because you have really nice instructive methods.
Thanku you sir great job!!
Amazing video!
Wow good explanation
Please make more..similar videos further.. I apreciate
Very clear and helpful for rookies like me...
Thank you. I appreciate it!
I’m with everyone else. Thank you and please do more FPGA videos! :)
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awesome my man. ur a fancy teacher
Thanks! I am anything but fancy but I’ll take it! Haha
Awesome thank you sir its very clear and interesting
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super good tutorial, thanks
Excellent clear video. Thank you so much for putting it together. You have a new sub :)
I need a fpga therapist. Is someone here available? Why there is no more videos in this channel? the first one gives me the impression that this therapist is really good! :D
Thanks! I do think we all need a little FPGA therapy every so often. They're just so time-consuming to produce!
So good, thank you!
Thank you very much! Excellent starter tutorial!
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Brilliant! This is reallyyyyyyyyyyy helpful.
Excellent video!
Some suggestions:
Rather than specify the exact FPGA model, package, etc., it’s easier to specify the Digilent board name, which will set the FPGA parameters automatically.
Lastly, just a minor point-when calculating the current through the LED you forgot to account for the forward voltage drop of the LED, which for a green LED is ~2 volts. So the current is (3.3 - 2.0)/R.
Hi Jerry, thanks for your thoughtful comments! I originally intended to do as you suggest, but decided it would be more valuable to walk the students through the process so they could understand what those options mean. Certainly, in later classes, I have students create projects for pre-defined boards (which is much simpler!)
Also, I realised shortly after uploading the video that I didn't take into account the forward voltage drop across the LEDs. Oops!
Have a wonderful weekend and thanks again.
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Hey your name fpga therapy is great, I was a bit stressed with being stuck with my fpga and seeing this helped feel better. However I thought to finish projects you always need to combine them with Vitis (SDK before) and TeraTerm but now you just did it with only Vivado?!
Hi Silvercat4, I'm glad you felt at ease after watching this video. FPGAs are beautiful, but they do take time to understand. After that, it's great!
If you want to program a MicroBlaze core or the processing subsystem (PS / CPU) on a system-on-chip FPGA (e.g., a Zynq) then Vitis is useful. As for TeraTerm, I think any terminal/emulator will work.
If all you want to do is configure the programmable logic (PL / FPGA) then you just need Vivado. There's a lot that can be learned before bringing MicroBlaze or a PS into the mix! :)
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I appreciate the articulate explanations and lack of heavy accent.
Great work man! Please make some new videos if you can find the time!
Thanks, Rob. I appreciate it! I plan to produce a few more videos using similar (entry-level) FPGA platforms. If there's a topic you'd like me to cover, please let me know.
I have a vcu1525 that I am trying to figure out, this gave me some much needed direction. Especially your comparison of synthesis to compiling.
@@fpgatherapy I am trying to port an application written in C++ to the VCU1525, maybe a tutorial on the workflow of converting a simple c++ program to a bitstream? Are you aware of any significant workflow differences that I should be aware of when working with the VCU?
@@robmartin7873 That's a very powerful development kit. There are considerable workflow differences between conventional 'software' development (e.g., C, C++) and FPGA development. I find that the more experienced you are at software, the more difficult it is to build the intuition for how your code is translated into a functioning program (or bitstream) on the FPGA. It's important to understand how the synthesis and implementation tools translate your code into basic logic elements. I've also found that a lot of students take some time to get used to the fact that everything is happening all the time on the FPGA, and not necessarily in a defined sequence.
Ultimately, translating a software algorithm onto an FPGA often depends on a) the nature of the algorithm (e.g., signal processing vs. pure logic vs. a procedural, etc.); b) your specific goal (performance, functionality, parallelization, determinism), and c) how patient you are.
When did you begin with the ZCU?
@@fpgatherapy We got our hands on the VCU back in the summer of 2018, we quickly discovered that we were in way over our heads, and hired an FPGA dev, he spent 3 months on the project and stated that he could not overcome some kind of library issue. So the project has been dormant for a few months, however it bothers me having such a powerful piece of equipment sitting idle. Do you offer consulting services by chance?
Hi, thank you for uploading this nice explanatory tutorial. Can you make a video of a design using differential clock of virtex - 7 board in constraint file. I have trouble in generating differential clock of the board and connect it with the design. Thanks
Hi Naveen. I had planned this out, actually, and have some code ready that may be of some help prior to me releasing a new video.
Your FPGA will have positive and negative (differential) clock pins on it. In your constraints file, you need to specify the pin locations and IO standards according to your development board's datasheet. It might look something like this (for a ZCU104 Zynq UltraScale+ development board):
set_property PACKAGE_PIN E23 [get_ports "CLK_125_N"]; # Bank 28 VCCO - VCC1V8 - IO_L13N_T2L_N1_GC_QBC_28
set_property IOSTANDARD LVDS [get_ports "CLK_125_N"]; # Bank 28 VCCO - VCC1V8 - IO_L13N_T2L_N1_GC_QBC_28
set_property PACKAGE_PIN F23 [get_ports "CLK_125_P"]; # Bank 28 VCCO - VCC1V8 - IO_L13P_T2L_N0_GC_QBC_28
set_property IOSTANDARD LVDS [get_ports "CLK_125_P"]; # Bank 28 VCCO - VCC1V8 - IO_L13P_T2L_N0_GC_QBC_28
You'll also want to specify that CLK_125_P is a clock (it will propagate this information for CLK_125_N). Do this with some code in the constraints file like this:
create_clock -period 8.000 -name CLK_125_P [get_ports CLK_125_P]
Note: '-period 8.000' specifies the clock's period in nanoseconds. The ZCU104's clocks have a frequency of 125 MHz, so the period is 8.000 ns.
Place this create_clock command above the set_property commands in your constraints file.
If you want to generate a single-ended clock based on your differential input clock, you should use an IBUFGDS (stands for input buffer, global differential signal) in your top-level VHDL or Verilog file.
IBUFGDS #(
.IOSTANDARD("LVDS") // Specify the input I/O standard
) IBUFGDS_inst (
.O(clk), // Buffer output
.I(CLK_125_P), // Diff_p buffer input (connect directly to top-level port)
.IB(CLK_125_N) // Diff_n buffer input (connect directly to top-level port)
);
You could test this out in Verilog with the following code (in addition to the constraints file you'll need to create):
module clockCreation_TOP(
input CLK_125_N,
input CLK_125_P
);
wire clk;
IBUFGDS #(
.IOSTANDARD("LVDS") // Specify the input I/O standard
) IBUFGDS_inst (
.O(clk), // Buffer output
.I(CLK_125_P), // Diff_p buffer input (connect directly to top-level port)
.IB(CLK_125_N) // Diff_n buffer input (connect directly to top-level port)
);
// Example clocked process using the newly generated clock
reg [31:0] counter;
always @(posedge clk) begin
counter
Time 18:09: You said there are "anode connected resistors". Actually, they are cathode connected.
Great tutorial. How can I activate all the leds on one of the 7-segments led display?
Thanks a lot!
YOU DA MAN
Hey Brother, firstly great Video. Why have the videos stopped? I have a ZC706, needed help with storing my verilog code in memory so when the power goes off it doesn't forget everything. Couldn't find any more of your videos.
@FPGA Therapy I am running a Zynq on the Zybo dev board. I would absolutely love to see you do a video fixing errors. I am currently having trouble fixing a "no such directory"/"could not read file error , yet the directory and file do you exist. This was while using Vivado IDE just before generating a bitstream. I think it has something to do with generating the design constraints and creating IOSTANDARD constraint ".../axis gpo 0/gpo io o[0]" not directly connected to top level port. Nevertheless a tutorial on the TLC console and output messages and solving errors we would be most appreciated. You do an excellent job explaining.
Want to learn how to develop an fpga?
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I had this problem come up once ‘could not read file’, it seemed to be to do with Windows file path length - I was using Microsoft Onedrive at the time. The problem went away after I transferring the project directory to the local hard drive.
Which one is cheapest FPGA for students that can be programmed through a USB from PC?
how to write the xdc file if the input range in the form of [63:0]A like this, can you please tell me sir,
Thanks in advance.
How did you actually kick off the synthesis? That step is not visible. How did you get to the "launch Runs" screen?
Great question! On the left hand side of the Vivado window (in the Flow Navigator panel) there is 'Run Synthesis' button.
Please make more videos!
Hai , I have a problem in synthesis the program .It kind of license not founded for fueatre synthesis
But I properly put license
What can I do
Unfortunately there are many reasons this could happen. Are you running Vivado on Linux or Windows? I'm sure by now you've solved this problem. Good luck in the future.
Can't we use GUI to assign the top level port to IO pins with specific voltage standards? What about timing contstraints, where is that done?
You can, but it's good to define the IO constraints manually in tcl. It also allowed me to demonstrate how to use the data sheet to answer the unknown questions about IO voltage standards etc.
@@fpgatherapy everything goes into the XDC file?
Why you have not uploaded more tutorials on channel?
Great video! Questions: Why didn't the output port appear in the verilog file? Also, I always end each constraint with a semi-colon, is this no longer required?
Thanks!
Hi Curtis, I discovered soon after putting this video together that I failed to press 'enter' after typing in the name for the output port.
As for terminating constraints / lines in Tcl, you can use a semicolon if that's your style, but it's not strictly necessary because a new line has the same effect. I have not tried multiple constraints on a single line separated by semicolons, but I imagine this would be valid as well.
Thanks for your support and encouragement.
Lyle
How do you get the speed grade when selecting the part? I've been looking through the box of the board, but I haven't found anything regarding the speed.
Hi AnMoMu,
If you go to 2:54 on the video you'll see a close up of the FPGA chip. This close up picture shows the device family Artix-7, part number (XC7A100T) and package identifier (CSG324). The line below the package identifier is the 'Lot Code' (useful for traceability and verification of the part). Then, immediately below the Lot Code is a number (1) and letter (C). The number '1' indicates the device speed grade (in this case, the higher the number, the faster the FPGA's minimum performance in terms of clock speed... i.e., higher speed grade -> faster designs). The letter indicates the device's temperature grade (C = Commercial, I = Industrial, and E = Extended).
The Nexys-4 DDR's Artix-7 has a speed grade 1 and temperature grade C.
Note: it's unlikely you'll find a development board with a temperature grade other than C, but perhaps some boutique reference boards do.
I hope this is helpful.
@@fpgatherapy It's been really helpful. Thank you very much.
I've gone through your channel......it's quite disappointing to see a single video. Please do other video's on FPGA
@Jitesh Prasad What do you need help with?
Want to learn how to develop an fpga?
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Can you also make a Video about building a reusable space rocket with FPGA? pls need help ASAP
At my current video production rate, you'll probably get it in about 1000 years or so! =)
Can I get a video of converting c or c++ code into vhdl code in vivado
nice!!!!!!!!!!!
help with more verilog coding sir
thx , where are u ?)
Thanks, I'm in Australia.
haha, the last sentence
Brilliant! Save me from digital lab!!!
The downvotes are all designers of unnecessary GUI feature designers in Vivado