Generating custom AXI4-Stream IP core using Xilinx Vivado
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- เผยแพร่เมื่อ 24 ก.พ. 2020
- #Vivado #AXI4Stream #CustomIP #ImageFiltering
The source code can be found here.
github.com/vipinkmenon/imageF...
There is a minor error in the code shown in the video which is corrected in the repository and explanation is given in the following Video
• Developing application...
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Excellent video explaining AXI Streams and how to implement your own. Thank you.
Excellent, thank you very much !this project is very useful for me !
Thank you for the great video sir.
it's very useful! thank u so much
24:17 I think mvalid
Very useful, thanks!
29:41 How will m_axis_valid delayed by 1 clock cycle? as the inversion and assertion of m_axis_valid are in separate blocks both will be entered at the same time right. Can you please correct me if I am wrong.
Hello Vipin,
Thanks for the explanation..
I have two separate axidma read_channels connected to two pl ddr4's..How to trigger(start) both the dma channels at same posedge?
Thank you.
Sir, at 3:26 is data transferred during 200, 400, 600 ns ? To me it seems so, since both "valid" and "ready" is high. Correct me if I am wrong.
This is a great video, may I ask why we cannot directly assign 32 bits input signal to an 32 bits output reg, but using a for loop do process 8-bit by 8-bit?
That is correct. If you look at my subsequent videos, that is how it is done. But there is a reason why it is like that in the Xilinx template. For AXI interface, there is an optional signal called KEEP. Using this signal you can choose which in a register which data should be changed and which should be preserved. 1 bit in KEEP represent 1 byte in axi data. So for a 32 bit data interface, there will be 4 bit KEEP. If the keep value is 'b1111 all the data will get stored in the register. If it is 0111, the upper most byte in the data shouldn't be written into the register but only the lower 3 bytes. So on and so forth. That is why Xilinx using that for loop instead of using a if else if or a case statement. For loop is more scalable in this case since the data width can be any multiple of 8
Hello sir. Since the Slave is just an interface, how does it do inversion.
at 14:00 why are we taking the particular signals as slave or master what is the criterion?
you can always accept new data when m_axis_valid is low, independent of anything else.
Your slide about what is master is inaccurate. Master is not determined by receiving or writing data, but whether it initiates a transmission. DMA controller can also read data from DDR memory, say, in which it is still a master, not a slave.
Hi, do you have any videos for making axi memory map?
There is a video on designing AXI lite device. In the neural network design also AXI Lite core is used
Sir Its a great video... clearly understandable. But I have some doubts in this. As per the concept data transmission should take from master to slave , but in this video you have written code the code for slave to master. means you are inputting data at slave and sending it to master. How is possible? would you not mind to explain it please?
It will be incorrect to say whoever transmits data is called a master. Generally a master is defined as the entity who initiates a transaction. That transaction can be read or write. In case of write master will just write and in case of read master will initiate the read option and slave will send the data. This is especially the case in AXI4 interface. In axi stream, yes the module which sends data out we will say has a master interface and the one which gets the data we say has a slave interface. It is very much possible same module has both master and slave interface. That is what is happening here. The customer IP has a slave interface, through which it receives data and sends out the processed data through the master interface.
@@TheVipinkmenon Understood sir... thanks alot
@@TheVipinkmenon if either slave or master can receive and send then why is the send part here the master? I get that master initiates so is it because if its slave it won't be able to send data if it's done with processing it? would making the output part slave and having a done line to processor be an alternative to this? like whenever done is high master can receive the data and then confirm it back to slave to send next data?
your videos and contents are greatttt but the organization of videos is quite poor if you can work on that i think this channel can go a long way!
Exam questions be like:
@4:00: Please indicate whether or not the data transfer is valid at the following three timesteps: 300ns, 500ns and 700ns.
Like the fuck am I supposed to do with the third one???
For anyone else also confused by this bad timing diagram, you should be. Instead check out the timing diagrams in the AXI manuals regarding the VALID and READY signals, they're very well explained and not ambiguous like they are in this video.
Indeed, this video presents an ambiguous timing diagram where a signal is both changed on the same edge that it is being sampled, which can cause a setup or hold time violation, as well as ambiguity in interpretation.
I've seen this in many slides in my university and it bothers me because it's very confusing for students. What if the signal changes state very slightly earlier, or slightly later? The entire behavior of the circuit is changed