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Very nice! Just what I wanted to read up this weekend.
Very good and clear explanation. Thanks. Hope you will make more exercises like this. Very helpful :)
Thank you for this very good demo
Thank you for your demo, well explained
Cheers for your awesome tutorial!
The sound is very low
Please upload more vids
Thanks!
What to do if I want to monitor axi signals?
Why did you run VITIS here? It was not necessary to show the use of ILA.
He uses the Zynq processing clock (FCLK_CLK0 and FCLK_CLK2) to drive the counter and the ILA. Therefore he has to start the Zynq processor to configure and start the clocks. This is done by running the debugger in Vitis.
Very nice! Just what I wanted to read up this weekend.
Very good and clear explanation. Thanks. Hope you will make more exercises like this. Very helpful :)
Thank you for this very good demo
Thank you for your demo, well explained
Cheers for your awesome tutorial!
The sound is very low
Please upload more vids
Thanks!
What to do if I want to monitor axi signals?
Why did you run VITIS here? It was not necessary to show the use of ILA.
He uses the Zynq processing clock (FCLK_CLK0 and FCLK_CLK2) to drive the counter and the ILA. Therefore he has to start the Zynq processor to configure and start the clocks. This is done by running the debugger in Vitis.