Vivado and Vitis

0:00 Introduction
8:44 Introduction to block design and hardware configuration
29:34 Preparing and generating a bitstream
42:58 Introduction to Vitis and exporting from Vivado
47:52 Example Vitis project

[@francofong]

Thanks!

[@iyyappanr957]

Nice tutorial.. Can you tell me which debugger are you using for programming and debugging in this video? Which one is good to use for multiple CPU's and FPGA core debugging?

[@Priyajit_Ghosh]

what is the 220 course that's mentioned in this video?

[@vijaysakre5798]

Hello,
Can I have the working code for the vitis please

[@curtisnotestine3134]

Did you find the error? What was the fix?

[@johnjj2637]

For one thing, he used _BASEADDR instead of _DEVICE_ID with XGpio_Initialize().

[@renshortbull7536]

In addition to John's comment, use 1 for the GPIO Channel.

[@renshortbull7536]

It turns out you can see the completed code at the beginning of the BYU Computing Bootcamp Vitis HLS video.

[@fernandoi8958]

58:03 this indentation is a test to my ocd...

[@user-bj3qh4nl1k]

47:00