ZYNQ for beginners: programming and connecting the PS and PL | Part 1
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- เผยแพร่เมื่อ 16 ก.ค. 2024
- Part 1 of how to work with both the processing system (PS), and the FPGA (PL) within a Xilinx ZYNQ series SoC.
Error: the "NANDgate" verilog file i wrote was supposed to be titled "ANDgate," but functionally was the same :p sorry for the goof
Link for Part 2: • ZYNQ for beginners: pr...
Thanks for watching! - วิทยาศาสตร์และเทคโนโลยี
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I really appreciate you in not only explaining what you are trying to do, but also explaining other terms and buttons and features surrounding what you are trying to do to help get a bigger picture of why and how we are this thing in vivado. thanks
Thanks for watching and your comment :)
Great video, there's nothing else online that is as introductory and easy to understand as this video. In fact San Diego State University is instructing their students to watch this to learn how to work with the minized board with has both PS/PL As well. So thanks.
wow i am so happy that it is working! thanks for the feedback and for watching!
Thank you very much.
I have followed both videos exactly as explained and changed the .xdc file of ZedBoard and it's working perfectly.
Many thank for your useful video. I have been looking a while for a video that has both PL and PS code. I hope we could see more videos like this in the future.
Brilliant video. Really appreciate it. No other material on youtube explained it so easily. I could apply the same principles to my PYNQ boards.
Thank you very much, This is exactly what I´ve been looking for.
Great! I am glad it helped!
Great work Dom, a nice beginner tutorial
About 12:20 in, the S_AXI options did not appear. I had to select GPIO or the OK button would not appear. When I completed the Block Automation, the M_AXI_GP0_ACLK input disappeared.
Not to worry though, just open up the Zynq Processing System block and edit the properties to enable the GP0 AXI. Then it worked just fine. I've already seen Part 2, which this is a setup for. This stuff is pure gold! You have to fish through a lot of documents to find what these two videos show. Thank you very much Dom.
I am glad you got it working!! Thanks for the positive feedback!!
I was having this exact problem and your comment as ell as solution was exactly what I needed to resolve my issue, Thank you
Thank you! I keep seeing too many PS examples using software. The sight of that "RTL" block in the bock diagram is a subtle, but beautiful thing. That's where the magic happens.
You are so right!! Thanks for the comment!!
Thank you so much for this video as it really stabilized my shaky basics.
Thank you for great video and clear explanation 🙏
This is an awesome video, thanks
Wow! Amazing I was looking for this kinda tutorial.. please make it more for us.
Im very glad that you found it helpful!
Exactly what I'm looking for. You da man!
Thank you! Useful videos!
I am happy you like them!
Hi, Thank you for the video Dom.
I wanted to know that what max. Speed of IO-PIN of Micro-Zed Board with 7020?
I cannot find this information into the datasheet. Can you please help me out here
great stuff, good explanation.
Great Video, Well explained 10/10
Hi, Thank you for the tutorial. Very cool. I have one worry, I could not "Add Module to Block Design". What do you think is the problem? the error message mentioned the port type led0 is not recognized. Only std_logic and std_logic_vector types are allowed for ports.
Hi dom, will you do more tutorials on the zynq fpga?
Thanks for the tutorial! Should it also work when i use the latest vitis version? i dont get it managed that it works...
Very helpful ,thank u
could you explain how to greate a board file snd how to defind MIO? Thanks.
Thanks for the nice video and explanation. I have a problem generating bitstream, it says ERROR: [DRC NSTD-1] Unspecified I/O Standard: 3 out of 133 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. I searched some sources but could not fix it. Could you help ?
Good One!
Thank you for the video, very useful for beginners. Can you upload a video on how to write data into DDR memory using RTL data from PL.
Audio quality was fine.
In our design, axi i2c ip is continuously generating interrupts as soon as we load pl file. Any suggestions
love yr style
Finally, someone is explaining this connection, well done!!! Could you please tell me why the option "add module to block design" is greyed out in my program?
maybe u have it in systemVerilog file? because for me it is only work for verilog
Please make tutorials on the vivado software for ZC706 board
How you can use the RTL instantly at 10:58? There have no such option for me in Vivado 2015.1 or it only available for Vivado 2019
?
Best tutorial
great video , thank you verry much
😉😉😉
Hello!! What should we do if there are 2 outputs?
Excellent video, could you do tutorials using a Zedboard and Vivado from 0?
so here AND gate giving one output signal. what to do if i need all four combination on input for operating four different code in PS part?
@9:03 you should not use RGB LEDs with 100% driven output, they should be at 50% PWM duty cycle max. Below that section (as seen in video) was the standard LEDs for Arty-Z7 that are safe to drive 100%, thanks for video this answered many questions I had.
gotcha thnks
That's interesting. Why not?
Having seen this video, I am about to start with a Cora-z7 board, which has two rgb diodes on it, useful as indicators. In beginner projects I do not run them off PWM, I just set them to '1'. I only use them to test button presses etc, should I not be doing this? Seems a bit strange...
But if need be I'll write a PWM entity to drive them.
BTW, many, many thanks to Dom, this was perfect and exactly at the level needed!
@@alexgian9313 IIRC my information came from the documentation for the Arty-Z7 I refer to. Maybe your Cora-Z7 hardware design is different, such as having higher ohm inline resistors in the wiring diagram. LEDs can be made to shine brightly with differing MTBF figures.
@@DM-fw5su Thanks for that, the Arty and Cora setups look very similar, I'll see if I can find anything in the spec sheets.
sir how to run the python on zinc and how to build own fpga for runinng python
great. thx.
Wow!!! Thanks!
I am working with Zybo Z7-10, not Arty like you, but I managed to find constraint masterfile and other prerequisites... Everything else is pretty much the same. But I get these warnings(after I create HDL wrapper), and I don't know what they mean. Can someone explain?
CRITICAL WARNING: [PSU-1] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.050 . PS DDR interfaces might fail when entering negative DQS skew values.
CRITICAL WARNING: [PSU-2] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.044 . PS DDR interfaces might fail when entering negative DQS skew values.
CRITICAL WARNING: [PSU-3] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 has negative value -0.035 . PS DDR interfaces might fail when entering negative DQS skew values.
CRITICAL WARNING: [PSU-4] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 has negative value -0.100 . PS DDR interfaces might fail when entering negative DQS skew values
The parameter PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_n should always be positive I believe because it if is negative it means data is arriving late. Does your master constraint file contain timing constraints? If so, try deleting those and just using the physical constraints for now.
I assume the "ZYNQ" thing is the PS, right? But usually isn't there multiple CPUs (maybe corext A53, cortex R5 for example ) in the PS and how does the "ZYNQ" know which one to use to do the "NOT" operation?
The ZYNQ is the processor, just like a Cortex A53 is a processor. There arent multiple processors on a ZYNQ chip unless you instantiate them in the block design/code. (You can put arm processors onto xilinx chips). ZYNQ is the name of the chip family as well as the name of the processor on the chip, so when you are programming a ZYNQ chip in C (not the FPGA part), then you are programming the ZYNQ processor
@@Dom-bo8wd I see. I just go to the xilinx website and happen to find one of "ZYNQ" processor called "ZYNQ UltraScale+ CG" ("www.xilinx.com/products/silicon-devices/soc/zynq-ultrascale-mpsoc.html"). However, according to description of "ZYNQ UltraScale+ CG", it contains both "cortex A53 and cortex R5", so the "ZYNQ" is not a processor like A53 in this case? It is kind of confusing that the description says that it has both A53 and R5.
Okay i understand now. Yes the zynq i was using in the video is just a ZYNQ 7000 series which only has one type of processor. The ZYNQ ultrascale chips have multiple processors on board. I am sorry I should have made that clearer.
@@Dom-bo8wd Yes, I see. It is clear now. Thank you. And in this case, if there are multiple processors in the ZYNQ, there should be an option to choose which one to run the c code in the sdk environment, right? I remember that in the sdk environment, after clicking "new" -> "application project", there should be a field that show the CPU name (I assume that user should be able choose one of the CPU (A53 or R5) if there are more than 1 CPU in there, right?).
VHDL is not case sensitive, but I adhere to writing code like it were. I don't know if Viviado or Verilog are case sensitive. If someone would comment on this, I'd be grateful. Thanks!
Verilog is case sensitive. Here is a link to a paper on some subtleties about the language www.google.com/url?sa=t&source=web&rct=j&url=lcdm-eng.com/papers/snug06_Verilog%2520Gotchas%2520Part1.pdf&ved=2ahUKEwiv-7uiwq7uAhXGUt8KHRJVDbIQFjACegQIDBAB&usg=AOvVaw03cv3_MkZV2pnkMtmieTX9
@@Dom-bo8wd Thanks a lot Dom!
Thank you, great friendly tutorial. But can't we just run the NOT and the AND on the FPGA ? To avoid doing the C code on SDK?.
What is the purpose of the processor in this FPGA? Will it not introduce delays if we gonna make a real time system ? Thank you
Hi! Yes you can run the NOT and the AND on the FPGA, and it would probably be faster. The purpose of the video is only to show how to connect the processor and the FPGA for learning purposes.
Can you wire external 5/0 v digital inputs to the mod pins instead of using their buttons and switches?
Yes, but you HAVE to use a level shifter. I have done this before with arduino to the FPGA but you need to step the voltage down to 3.3 V before input to the FPGA board.
@@Dom-bo8wd thanks Im trying to put together and encoder for my ADC and i figured that a step down is needed I just wasn't sure if it was possible in the xdc i/o file but I'm going to play around with it. Excellent video by the way, do you have a patreon?
@@michaelbradley7621 ah gotcha, yes I think you can set different voltage levels in the xdc file, but I have never seen a 5V setting. Vivado might yell at ya lol. No patreon, maybe I will set one up in the future :)
This is the same as transferring data from ps to pl?
Yep. I think there is more than one way but you can do it this way
@@Dom-bo8wd And let me ask one more question. Are you using PS internal memory(cache) to send data? Means you press swich then put into internal memory(cache) PS then put out LED?
Bla bla bli bli bu 😅
Sorry I just can’t get over the fact that a NAND gate should be less transistors than an AND gate
Many thanks for your great videos.
I got 3 errors after Launching the Runs at "Generate bit stream".
Btw your launch box is 2 jobs mine is 4 jobs, nevertheless I redid it again like yours and still get errors, I couldn't find a solution, can you help me out here?
1- [DRC UTLZ-1] Resource utilization: BIBUF over-utilized in Top Level Design (This design requires more BIBUF cells than are available in the target device. This design requires 260 of such cell types but only 130 compatible sites are available in the target device. Please analyze your synthesis results and constraints to ensure the design is mapped to Xilinx primitives as expected. If so, please consider targeting a larger device.)
2- [DRC UTLZ-1] Resource utilization: PS7 over-utilized in Top Level Design (This design requires more PS7 cells than are available in the target device. This design requires 2 of such cell types but only 1 compatible site is available in the target device. Please analyze your synthesis results and constraints to ensure the design is mapped to Xilinx primitives as expected. If so, please consider targeting a larger device.)
3- [Vivado_Tcl 4-23] Error(s) found during DRC. Placer not run.
Many thanks for your time :-)
The reason mine says 2 jobs is because i am only running a dual core cpu, where you probably have quad core. From your errors it looks like you might be using a different zynq chip maybe one with only a single core arm processor? Thats possibly why the error tells you there is only one ps7 available. Or maybe you accidently tried to instantiate two copies of the zynq processor?
@@Dom-bo8wd Thanks!
Quite explanatory, thanks for that but please don't say bla bla bla :)
PS is ASIC, it is not programmable gate array like PL part
Oh, really? I actually asked a question in the comments if the PS is like an application processor like Cortex A53 or so, and as such, if he used an SD card with Linux on it to run on the Cortex A Processing System.
@Dom-bo8wd this walkthrough is really really excellent.
Glad you like it!
Hii! Great tutorial i wanted some help in my project how can I contact you?