Arjun Narula
Arjun Narula
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Voting Machine in Verilog (with code) | Verilog project | XILINX | EDA Playground
In this Verilog project, a Voting Machine has been implemented by Mr. Harman in Verilog HDL on EDA Playground.
Please do Like, Share and Subscribe for more such content.
Verilog Code
Other Projects-
►Traffic Light Controller in Verilog - th-cam.com/video/Yt7no6rwCVk/w-d-xo.html
►Round Robin Arbiter in Verilog - th-cam.com/video/X6oJn7r9-8s/w-d-xo.html
►Vedic Multiplier in Verilog - th-cam.com/video/6M3nyyQfpHU/w-d-xo.html
►Clock with Alarm in Verilog - th-cam.com/video/pTk1H50e8bI/w-d-xo.html
►Washing Machine in Verilog - th-cam.com/video/iAoi9jTzxcI/w-d-xo.html
►N bit Multiplier in Verilog - th-cam.com/video/lmzCdx6gkdU/w-d-xo.html
►PWM Shift Register in Verilog - th-cam.com/video/Pz9sPflKpXc/w-d-xo.html
►Vending Machine in Verilog - th-cam.com/video/tJc0blBDRzo/w-d-xo.html
►Hexadecimal Keypad Scanner in Verilog - th-cam.com/video/Y1cp2kwos5M/w-d-xo.html
►RAM - ROM Design in Verilog - th-cam.com/video/m18YU9xjETU/w-d-xo.html
0:00 Introduction
0:07 Intro & Agenda
3:28 Verilog Code
14:40 Testbench
15:40 Waveform
#verilog #verilogproject #arjunnarula #electronic #project
มุมมอง: 50 482

วีดีโอ

RAM and ROM design in Verilog | Verilog Project | EDA Playground19:35RAM and ROM design in Verilog | Verilog Project | EDA Playground
RAM and ROM design in Verilog | Verilog Project | EDA Playground
มุมมอง 21K2 ปีที่แล้ว
In this Verilog project, RAM and ROM memory design has been implemented by Mr. Kushagra in Verilog HDL on EDA Playground. Please do Like, Share and Subscribe for more such content. Verilog Code Single Port RAM - www.edaplayground.com/x/CjBu Dual Port RAM - www.edaplayground.com/x/QfhN ROM - www.edaplayground.com/x/iCVx Other Projects- ►Traffic Light Controller in Verilog - th-cam.com/video/Yt7n...
Verilog Project | Hexadecimal Keypad Scanner and Encoder | XILINX | Vivado16:46Verilog Project | Hexadecimal Keypad Scanner and Encoder | XILINX | Vivado
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มุมมอง 11K2 ปีที่แล้ว
In this Verilog project, Hexadecimal Keypad Scanner and Encoder have been implemented by Ms. Yukta Sachdeva in Verilog HDL on Xilinx Vivado. Please do Like, Share and Subscribe for more such content. Verilog Code - github.com/yuktaa21/Hexadecimal-Keypad-Scanner-using-Verilog Other Projects- ►Traffic Light Controller in Verilog - th-cam.com/video/Yt7no6rwCVk/w-d-xo.html ►Round Robin Arbiter in V...
Vending Machine in Verilog (with code) | Verilog Project | EDA Playground | Electronics Project15:29Vending Machine in Verilog (with code) | Verilog Project | EDA Playground | Electronics Project
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มุมมอง 32K2 ปีที่แล้ว
In this Verilog project, Vending Machine has been implemented in Verilog HDL on EDA Playground. Please do Like, Share and Subscribe for more such content. Verilog Code - github.com/Arjun-Narula/Vending-Machine-with-Verilog Other Projects- ►Traffic Light Controller in Verilog - th-cam.com/video/Yt7no6rwCVk/w-d-xo.html ►Round Robin Arbiter in Verilog - th-cam.com/video/X6oJn7r9-8s/w-d-xo.html ►Ve...
N bit Multiplier in Verilog (with code)| Verilog Project | Xilinx Vivado | Electronics Project8:00N bit Multiplier in Verilog (with code)| Verilog Project | Xilinx Vivado | Electronics Project
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มุมมอง 15K2 ปีที่แล้ว
In this Verilog project, N bit Multiplier has been implemented in Verilog HDL on Xilinx ISE. Please do Like, Share and Subscribe for more such content. Verilog Code - github.com/Arjun-Narula/N-bit-Multiplier-in-Verilog Other Projects- ►Traffic Light Controller in Verilog - th-cam.com/video/Yt7no6rwCVk/w-d-xo.html ►Round Robin Arbiter in Verilog - th-cam.com/video/X6oJn7r9-8s/w-d-xo.html ►Vedic ...
Verilog Project | PWM Shift Register | Xilinx Vivado | Electronics Project9:37Verilog Project | PWM Shift Register | Xilinx Vivado | Electronics Project
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มุมมอง 7K2 ปีที่แล้ว
In this Verilog project, a PWM Shift Register has been implemented by a friend of mine Mr. Aditya Agrawal in Verilog HDL on Xilinx ISE. Please do Like, Share and Subscribe for more such content. Verilog Code -github.com/Aditya2487/PWM_Shift_Verilog/tree/main Other Projects- ►Traffic Light Controller in Verilog - th-cam.com/video/Yt7no6rwCVk/w-d-xo.html ►Round Robin Arbiter in Verilog - th-cam.c...
Washing Machine using Verilog (with code) | Verilog HDL Project by @Dhaval Gupta | FSM | Vivado13:12Washing Machine using Verilog (with code) | Verilog HDL Project by @Dhaval Gupta | FSM | Vivado
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มุมมอง 25K2 ปีที่แล้ว
Hello everyone, In this Verilog project, a Washing Machine has been implemented by a friend of mine Mr. Dhaval Gupta in Verilog HDL on Xilinx ISE. Please do Like, Share and Subscribe for more such content. Verilog Code -github.com/Dhaval302/Washing_Machine_Automatic_HDL Other Projects- ►Traffic Light Controller in Verilog - th-cam.com/video/Yt7no6rwCVk/w-d-xo.html ►Round Robin Arbiter in Verilo...
Verilog HDL Project | Round Robin Arbiter(with code) | EDA Playground | Verilog22:09Verilog HDL Project | Round Robin Arbiter(with code) | EDA Playground | Verilog
Verilog HDL Project | Round Robin Arbiter(with code) | EDA Playground | Verilog
มุมมอง 16K2 ปีที่แล้ว
In this Verilog project, we will discuss and implement Round Robin Arbiter in Verilog HDL. It has been written and simulated by Mr. Aditya Mehta in an online simulator EDA Playground. Please find the Verilog code below: github.com/Arjun-Narula/Round-Robin-Arbiter Other Projects- ►Traffic Light Controller in Verilog - th-cam.com/video/Yt7no6rwCVk/w-d-xo.html ►Round Robin Arbiter in Verilog - th-...
HDL Verilog Project (with code) | Clock with Alarm | Xilinx Vivado8:30HDL Verilog Project (with code) | Clock with Alarm | Xilinx Vivado
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มุมมอง 20K2 ปีที่แล้ว
In this Verilog project Clock with Alarm has been implemented in Verilog HDL. Please find the Verilog code below: Github Link - github.com/Arjun-Narula/Clock-with-Alarm Other Projects- ►Traffic Light Controller in Verilog - th-cam.com/video/Yt7no6rwCVk/w-d-xo.html ►Round Robin Arbiter in Verilog - th-cam.com/video/X6oJn7r9-8s/w-d-xo.html ►Vedic Multiplier in Verilog - th-cam.com/video/6M3nyyQfp...
HDL Verilog Project | Vedic Multiplier (with code)| JDOODLE Online Compiler11:36HDL Verilog Project | Vedic Multiplier (with code)| JDOODLE Online Compiler
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มุมมอง 12K2 ปีที่แล้ว
In this Verilog project, a Vedic Multiplier has been implemented by a friend of mine Mr. Ayush Mahendru in Verilog HDL on an online compiler JDOODLE . Please do Like, Share and Subscribe for more such content. Links - Verilog Code -github.com/ayushmahendru03/hdl_8_bit Other Projects- ►Traffic Light Controller in Verilog - th-cam.com/video/Yt7no6rwCVk/w-d-xo.html ►Round Robin Arbiter in Verilog ...
Traffic Light Controller Using Verilog (with code)| Vivado| Moore Finite State Machine23:03Traffic Light Controller Using Verilog (with code)| Vivado| Moore Finite State Machine
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มุมมอง 65K4 ปีที่แล้ว
This is my first Verilog Project. It includes analysis and design of a T intersection traffic lights and then code is written in Verilog HDL language. PLEASE SUBSCRIBE TO THE CHANNEL!!!! GitHub link-github.com/Arjun-Narula/Traffic-Light-Controller-using-Verilog Verilog HDL Book-amzn.to/3K03Q7D Verilog with Digital Design - amzn.to/3K8Jt8n Other Projects- ►Traffic Light Controller in Verilog - t...

ความคิดเห็น

  • @varalakshmirathod3768
    @varalakshmirathod3768 20 วันที่ผ่านมา

    please give the code bro

  • @DarshanAchalkar
    @DarshanAchalkar 20 วันที่ผ่านมา

    How I would use it in modelsim Ise simulator Can i combine the modules in one module only

  • @nitinchinmay260
    @nitinchinmay260 21 วันที่ผ่านมา

    Why was the carry not considered at the adders.Anyone please respond?

  • @snehithreddy5576
    @snehithreddy5576 21 วันที่ผ่านมา

    How to display these projects on linkdin?

  • @Adi-tf9oc
    @Adi-tf9oc หลายเดือนก่อน

    what is need of synchronizer in the given circuit,what if we removed it

  • @narutofan429
    @narutofan429 หลายเดือนก่อน

    Which app using

  • @Gateprep2024
    @Gateprep2024 2 หลายเดือนก่อน

    where is the code link

  • @prakharawasthi1419
    @prakharawasthi1419 2 หลายเดือนก่อน

    thanks brother for descibe it in very simple manner.

  • @pranavreddy1245
    @pranavreddy1245 2 หลายเดือนก่อน

    how to simulate pls tell brother

  • @atikpathan9693
    @atikpathan9693 2 หลายเดือนก่อน

    Code??

  • @loveff9172
    @loveff9172 2 หลายเดือนก่อน

    thank you so much💗

  • @pranav_dance
    @pranav_dance 2 หลายเดือนก่อน

    Code pls

  • @shrivatsaparvatikar5423
    @shrivatsaparvatikar5423 3 หลายเดือนก่อน

    code of voting machine?

  • @kavya563
    @kavya563 3 หลายเดือนก่อน

    Could u please send the code

  • @pavansaikumar.m5653
    @pavansaikumar.m5653 3 หลายเดือนก่อน

    Sir, Could you please provide SPI and I2C projects.

  • @sayandeepdey4
    @sayandeepdey4 4 หลายเดือนก่อน

    can you please share the PPT

  • @alenjacob764
    @alenjacob764 4 หลายเดือนก่อน

    Bro eda playground is not supporting Icarus veriog 0.9.7 Please help

  • @abhirambhaskaran6010
    @abhirambhaskaran6010 5 หลายเดือนก่อน

    there is no code in description can you please send it

  • @dhimanshahil3502
    @dhimanshahil3502 5 หลายเดือนก่อน

    Plss provide code

  • @Jahnavi015
    @Jahnavi015 5 หลายเดือนก่อน

    Can u please provide the total code

  • @TravelandAdventure496
    @TravelandAdventure496 5 หลายเดือนก่อน

    where are you writing this codee

  • @MasterAnime-ps3yx
    @MasterAnime-ps3yx 5 หลายเดือนก่อน

    where is the code?

  • @sruthipinapati5851
    @sruthipinapati5851 5 หลายเดือนก่อน

    Please give code in description

  • @Sandeepyadav-zd9ei
    @Sandeepyadav-zd9ei 5 หลายเดือนก่อน

    Thankyou for 25 marks mini project 🧡⚡💥💥🔥

  • @MichaelJohnson-tj4kx
    @MichaelJohnson-tj4kx 5 หลายเดือนก่อน

    Source code?

  • @starshine12r
    @starshine12r 5 หลายเดือนก่อน

    How to showcase the project then? Just the code and waveform is enough ?

  • @tanujicr
    @tanujicr 5 หลายเดือนก่อน

    the code is missing mask_enable logic, when do you set it?

  • @nagachoudendra5361
    @nagachoudendra5361 5 หลายเดือนก่อน

    Bro counter and ps waveforms are not showing,please tell

  • @fevilpatel8457
    @fevilpatel8457 6 หลายเดือนก่อน

    insted of this code can we use this one "" module vm( input clk, input rst, input button_1, input button_2, input null, output reg led, output reg [2:0]ctr1, output reg [2:0]ctr2, output reg [2:0]ctr3 ); initial begin ctr1=0;ctr2=0;ctr3=0; end always @(posedge clk or negedge clk) begin if(rst) begin ctr1=0;ctr2=0;ctr3=0; end else begin if(button_1) begin ctr1<= ctr1 +1; led<= 1'b1; end else if(button_2) begin ctr2<= ctr2+1 ; led<= 1'b1; end else if(null) begin ctr3<= ctr3+1; led<= 1'b1; end else led<=1'b0; end end endmodule "" test bench : '"" module tb(); reg clk; reg rst; reg button_1; reg button_2; reg null; wire led; wire [2:0]ctr1; wire [2:0]ctr2; wire [2:0]ctr3; vm uut(clk,rst,button_1,button_2,null,led,ctr1,ctr2,ctr3); always begin #1 clk <= ~clk; end initial begin $monitor("vb=%3d,vc=%3d,vn=%3d,led=%b,rst=%b",ctr1,ctr2,ctr3,led,rst); button_1<=0; button_2<=0; null<=0; clk<=0;rst<=1; #2 button_1<=1; button_2<=0; null<=0;rst<=0; #1 button_1<=0; button_2<=0; null<=0; #2 button_1<=0; button_2<=1; null<=0; #1 button_1<=0; button_2<=0; null<=0; #2 button_1<=0; button_2<=0; null<=1; #1 button_1<=0; button_2<=0; null<=0; #2 button_1<=0; button_2<=1; null<=0; #1 button_1<=0; button_2<=0; null<=0; #2 button_1<=1; button_2<=0; null<=0; #1 button_1<=0; button_2<=0; null<=0; #2 button_1<=0; button_2<=1; null<=0; #1 button_1<=0; button_2<=0; null<=0; #2 button_1<=0; button_2<=0; null<=1; #1 button_1<=0; button_2<=0; null<=0; #2 button_1<=0; button_2<=1; null<=0; #1 button_1<=0; button_2<=0; null<=0; #2 button_1<=1; button_2<=0; null<=0; #1 $finish; end endmodule ''' i have implemented the voting machine by using simple logic so can you please remark this and check it kindly reply .🙏🙏

  • @sachintom5971
    @sachintom5971 6 หลายเดือนก่อน

    will this code work on xilinx vivado

  • @_VISHNUPRIYAK-hc5si
    @_VISHNUPRIYAK-hc5si 6 หลายเดือนก่อน

    I have a doubt bro...Can I do this as a project or Should I have to improve this project for my paper presentation ?

  • @kavanakrishna3787
    @kavanakrishna3787 6 หลายเดือนก่อน

    Bro, can you please help me with the verilog code for 64KX 8 Rom???

  • @ajaymehrotra5931
    @ajaymehrotra5931 7 หลายเดือนก่อน

    can you please provide the code for this PWM shift register, in video it's not properly arranged.

  • @BharathKumar-w8t8m
    @BharathKumar-w8t8m 7 หลายเดือนก่อน

    Hi sir great explanation sir Can u send me the documentation and ppt sir

  • @ananyag6189
    @ananyag6189 8 หลายเดือนก่อน

    Please give the link for vending machine code... 😢 Its not there in the discription

  • @gowrikulkarni8340
    @gowrikulkarni8340 9 หลายเดือนก่อน

    when i run this code it is showing error

  • @debasishkar761
    @debasishkar761 9 หลายเดือนก่อน

    IN the GITHUB code I am seeing this signal is not driven "mask_enable" but used as a load.

  • @014-kotlasrinithareddy5
    @014-kotlasrinithareddy5 9 หลายเดือนก่อน

    Super explanation

  • @AmanGupta-zy2mj
    @AmanGupta-zy2mj 9 หลายเดือนก่อน

    Thanku so much sir. Great explanation sir

  • @tallasravani7055
    @tallasravani7055 9 หลายเดือนก่อน

    code can be explained good

  • @user-jt9uq6re3e
    @user-jt9uq6re3e 9 หลายเดือนก่อน

    In testbench code it is not working for other inputs other than you have given can you please tell me that how to clear that

    • @ankur6098
      @ankur6098 9 หลายเดือนก่อน

      did you implement the state machine..?

    • @user-jt9uq6re3e
      @user-jt9uq6re3e 9 หลายเดือนก่อน

      @@ankur6098 how to implement that ??? Please tell me

  • @runcongkuang7965
    @runcongkuang7965 9 หลายเดือนก่อน

    Thanks for your wonderful explanation. However, I can't find the logic of mask_enable in the code. Do you miss that?

  • @squirrelsvid1856
    @squirrelsvid1856 9 หลายเดือนก่อน

    Arjun , how to extraxt files from github and use it in vivade? Any video on that?

  • @TejasBhaskarJagtap-ex3wo
    @TejasBhaskarJagtap-ex3wo 9 หลายเดือนก่อน

    Good Project & Nice Explanation 👍

  • @hgameryt6151
    @hgameryt6151 10 หลายเดือนก่อน

    Cant find the code but the project is extrodonary bro

  • @heyitsmea8883
    @heyitsmea8883 10 หลายเดือนก่อน

    Why is address bit is 6? I didn’t get. Can u elaborate please

  • @user-fc8iu9zn4t
    @user-fc8iu9zn4t 10 หลายเดือนก่อน

    from where does mask enable value come ?

  • @saaho-m
    @saaho-m 11 หลายเดือนก่อน

    can u show me the rtl schematic diagram for this project

  • @tarakasuryashashank1267
    @tarakasuryashashank1267 11 หลายเดือนก่อน

    please show how to implement in spartan fpga board ? how to check inputs and outputs 🙂

  • @aakashsarma8480
    @aakashsarma8480 11 หลายเดือนก่อน

    If I am simulation using the modelsim software to simulate the code, how can I give the input in the modelsim software in decimal format.