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Arjun Narula
India
เข้าร่วมเมื่อ 18 เม.ย. 2020
An Electronics enthusiast
Voting Machine in Verilog (with code) | Verilog project | XILINX | EDA Playground
In this Verilog project, a Voting Machine has been implemented by Mr. Harman in Verilog HDL on EDA Playground.
Please do Like, Share and Subscribe for more such content.
Verilog Code
Other Projects-
►Traffic Light Controller in Verilog - th-cam.com/video/Yt7no6rwCVk/w-d-xo.html
►Round Robin Arbiter in Verilog - th-cam.com/video/X6oJn7r9-8s/w-d-xo.html
►Vedic Multiplier in Verilog - th-cam.com/video/6M3nyyQfpHU/w-d-xo.html
►Clock with Alarm in Verilog - th-cam.com/video/pTk1H50e8bI/w-d-xo.html
►Washing Machine in Verilog - th-cam.com/video/iAoi9jTzxcI/w-d-xo.html
►N bit Multiplier in Verilog - th-cam.com/video/lmzCdx6gkdU/w-d-xo.html
►PWM Shift Register in Verilog - th-cam.com/video/Pz9sPflKpXc/w-d-xo.html
►Vending Machine in Verilog - th-cam.com/video/tJc0blBDRzo/w-d-xo.html
►Hexadecimal Keypad Scanner in Verilog - th-cam.com/video/Y1cp2kwos5M/w-d-xo.html
►RAM - ROM Design in Verilog - th-cam.com/video/m18YU9xjETU/w-d-xo.html
0:00 Introduction
0:07 Intro & Agenda
3:28 Verilog Code
14:40 Testbench
15:40 Waveform
#verilog #verilogproject #arjunnarula #electronic #project
Please do Like, Share and Subscribe for more such content.
Verilog Code
Other Projects-
►Traffic Light Controller in Verilog - th-cam.com/video/Yt7no6rwCVk/w-d-xo.html
►Round Robin Arbiter in Verilog - th-cam.com/video/X6oJn7r9-8s/w-d-xo.html
►Vedic Multiplier in Verilog - th-cam.com/video/6M3nyyQfpHU/w-d-xo.html
►Clock with Alarm in Verilog - th-cam.com/video/pTk1H50e8bI/w-d-xo.html
►Washing Machine in Verilog - th-cam.com/video/iAoi9jTzxcI/w-d-xo.html
►N bit Multiplier in Verilog - th-cam.com/video/lmzCdx6gkdU/w-d-xo.html
►PWM Shift Register in Verilog - th-cam.com/video/Pz9sPflKpXc/w-d-xo.html
►Vending Machine in Verilog - th-cam.com/video/tJc0blBDRzo/w-d-xo.html
►Hexadecimal Keypad Scanner in Verilog - th-cam.com/video/Y1cp2kwos5M/w-d-xo.html
►RAM - ROM Design in Verilog - th-cam.com/video/m18YU9xjETU/w-d-xo.html
0:00 Introduction
0:07 Intro & Agenda
3:28 Verilog Code
14:40 Testbench
15:40 Waveform
#verilog #verilogproject #arjunnarula #electronic #project
มุมมอง: 63 389
วีดีโอ
RAM and ROM design in Verilog | Verilog Project | EDA Playground
มุมมอง 26K2 ปีที่แล้ว
In this Verilog project, RAM and ROM memory design has been implemented by Mr. Kushagra in Verilog HDL on EDA Playground. Please do Like, Share and Subscribe for more such content. Verilog Code Single Port RAM - www.edaplayground.com/x/CjBu Dual Port RAM - www.edaplayground.com/x/QfhN ROM - www.edaplayground.com/x/iCVx Other Projects- ►Traffic Light Controller in Verilog - th-cam.com/video/Yt7n...
Verilog Project | Hexadecimal Keypad Scanner and Encoder | XILINX | Vivado
มุมมอง 13K2 ปีที่แล้ว
In this Verilog project, Hexadecimal Keypad Scanner and Encoder have been implemented by Ms. Yukta Sachdeva in Verilog HDL on Xilinx Vivado. Please do Like, Share and Subscribe for more such content. Verilog Code - github.com/yuktaa21/Hexadecimal-Keypad-Scanner-using-Verilog Other Projects- ►Traffic Light Controller in Verilog - th-cam.com/video/Yt7no6rwCVk/w-d-xo.html ►Round Robin Arbiter in V...
Vending Machine in Verilog (with code) | Verilog Project | EDA Playground | Electronics Project
มุมมอง 39K3 ปีที่แล้ว
In this Verilog project, Vending Machine has been implemented in Verilog HDL on EDA Playground. Please do Like, Share and Subscribe for more such content. Verilog Code - github.com/Arjun-Narula/Vending-Machine-with-Verilog Other Projects- ►Traffic Light Controller in Verilog - th-cam.com/video/Yt7no6rwCVk/w-d-xo.html ►Round Robin Arbiter in Verilog - th-cam.com/video/X6oJn7r9-8s/w-d-xo.html ►Ve...
N bit Multiplier in Verilog (with code)| Verilog Project | Xilinx Vivado | Electronics Project
มุมมอง 18K3 ปีที่แล้ว
In this Verilog project, N bit Multiplier has been implemented in Verilog HDL on Xilinx ISE. Please do Like, Share and Subscribe for more such content. Verilog Code - github.com/Arjun-Narula/N-bit-Multiplier-in-Verilog Other Projects- ►Traffic Light Controller in Verilog - th-cam.com/video/Yt7no6rwCVk/w-d-xo.html ►Round Robin Arbiter in Verilog - th-cam.com/video/X6oJn7r9-8s/w-d-xo.html ►Vedic ...
Verilog Project | PWM Shift Register | Xilinx Vivado | Electronics Project
มุมมอง 8K3 ปีที่แล้ว
In this Verilog project, a PWM Shift Register has been implemented by a friend of mine Mr. Aditya Agrawal in Verilog HDL on Xilinx ISE. Please do Like, Share and Subscribe for more such content. Verilog Code -github.com/Aditya2487/PWM_Shift_Verilog/tree/main Other Projects- ►Traffic Light Controller in Verilog - th-cam.com/video/Yt7no6rwCVk/w-d-xo.html ►Round Robin Arbiter in Verilog - th-cam.c...
Washing Machine using Verilog (with code) | Verilog HDL Project by @Dhaval Gupta | FSM | Vivado
มุมมอง 29K3 ปีที่แล้ว
Hello everyone, In this Verilog project, a Washing Machine has been implemented by a friend of mine Mr. Dhaval Gupta in Verilog HDL on Xilinx ISE. Please do Like, Share and Subscribe for more such content. Verilog Code -github.com/Dhaval302/Washing_Machine_Automatic_HDL Other Projects- ►Traffic Light Controller in Verilog - th-cam.com/video/Yt7no6rwCVk/w-d-xo.html ►Round Robin Arbiter in Verilo...
Verilog HDL Project | Round Robin Arbiter(with code) | EDA Playground | Verilog
มุมมอง 18K3 ปีที่แล้ว
In this Verilog project, we will discuss and implement Round Robin Arbiter in Verilog HDL. It has been written and simulated by Mr. Aditya Mehta in an online simulator EDA Playground. Please find the Verilog code below: github.com/Arjun-Narula/Round-Robin-Arbiter Other Projects- ►Traffic Light Controller in Verilog - th-cam.com/video/Yt7no6rwCVk/w-d-xo.html ►Round Robin Arbiter in Verilog - th-...
HDL Verilog Project (with code) | Clock with Alarm | Xilinx Vivado
มุมมอง 23K3 ปีที่แล้ว
In this Verilog project Clock with Alarm has been implemented in Verilog HDL. Please find the Verilog code below: Github Link - github.com/Arjun-Narula/Clock-with-Alarm Other Projects- ►Traffic Light Controller in Verilog - th-cam.com/video/Yt7no6rwCVk/w-d-xo.html ►Round Robin Arbiter in Verilog - th-cam.com/video/X6oJn7r9-8s/w-d-xo.html ►Vedic Multiplier in Verilog - th-cam.com/video/6M3nyyQfp...
HDL Verilog Project | Vedic Multiplier (with code)| JDOODLE Online Compiler
มุมมอง 14K3 ปีที่แล้ว
In this Verilog project, a Vedic Multiplier has been implemented by a friend of mine Mr. Ayush Mahendru in Verilog HDL on an online compiler JDOODLE . Please do Like, Share and Subscribe for more such content. Links - Verilog Code -github.com/ayushmahendru03/hdl_8_bit Other Projects- ►Traffic Light Controller in Verilog - th-cam.com/video/Yt7no6rwCVk/w-d-xo.html ►Round Robin Arbiter in Verilog ...
Traffic Light Controller Using Verilog (with code)| Vivado| Moore Finite State Machine
มุมมอง 73K4 ปีที่แล้ว
This is my first Verilog Project. It includes analysis and design of a T intersection traffic lights and then code is written in Verilog HDL language. PLEASE SUBSCRIBE TO THE CHANNEL!!!! GitHub link-github.com/Arjun-Narula/Traffic-Light-Controller-using-Verilog Verilog HDL Book-amzn.to/3K03Q7D Verilog with Digital Design - amzn.to/3K8Jt8n Other Projects- ►Traffic Light Controller in Verilog - t...
aapke projects list main , when explaining the code or flowchart, voice is not properly amplifying , so its not much understandable . thank you
There is no code in the link u have provided could you please provide it
Can we implement this project in Xilinx vivado
can i implement this for 32bit multiplier
Great explanation sir. It would be really helpful if you share the code with us since its unavailable in the link description.
hey bro! i have doubt in it. would you please help me with it
Hello I am unable to get the rest of the wave forms how can I get that can you please or anyone tell me
How to simulate please tell me
Where these codes are found
can i add this in my resume?
Can we do this in xilinx vivado
did it work? i am starting doing on it
@shobhit9316 I didn't do it
Worst code ever. Are you kidding me?. Your code is not working properly for different inputs and you are presenting in TH-cam. Do you have any minimum knowledge how round robin arbiters work?
essss code ka link hoga tho b ejo
if initially all the requests are high i.e req0 req1 req2 and req3 , only output gnt1 is getting high
in discription code is not available provide the code
can you please provide the project code
your voice is not clear in the whole video.
Thank you , great explanation .
Do you have the code of it
please give the code bro
How I would use it in modelsim Ise simulator Can i combine the modules in one module only
Why was the carry not considered at the adders.Anyone please respond?
How to display these projects on linkdin?
what is need of synchronizer in the given circuit,what if we removed it
Which app using
where is the code link
thanks brother for descibe it in very simple manner.
how to simulate pls tell brother
Code??
thank you so much💗
Code pls
code of voting machine?
Could u please send the code
Sir, Could you please provide SPI and I2C projects.
can you please share the PPT
Bro eda playground is not supporting Icarus veriog 0.9.7 Please help
there is no code in description can you please send it
Plss provide code
Can u please provide the total code
where are you writing this codee
where is the code?
Please give code in description
Thankyou for 25 marks mini project 🧡⚡💥💥🔥
Source code?
How to showcase the project then? Just the code and waveform is enough ?
the code is missing mask_enable logic, when do you set it?
Bro counter and ps waveforms are not showing,please tell
insted of this code can we use this one "" module vm( input clk, input rst, input button_1, input button_2, input null, output reg led, output reg [2:0]ctr1, output reg [2:0]ctr2, output reg [2:0]ctr3 ); initial begin ctr1=0;ctr2=0;ctr3=0; end always @(posedge clk or negedge clk) begin if(rst) begin ctr1=0;ctr2=0;ctr3=0; end else begin if(button_1) begin ctr1<= ctr1 +1; led<= 1'b1; end else if(button_2) begin ctr2<= ctr2+1 ; led<= 1'b1; end else if(null) begin ctr3<= ctr3+1; led<= 1'b1; end else led<=1'b0; end end endmodule "" test bench : '"" module tb(); reg clk; reg rst; reg button_1; reg button_2; reg null; wire led; wire [2:0]ctr1; wire [2:0]ctr2; wire [2:0]ctr3; vm uut(clk,rst,button_1,button_2,null,led,ctr1,ctr2,ctr3); always begin #1 clk <= ~clk; end initial begin $monitor("vb=%3d,vc=%3d,vn=%3d,led=%b,rst=%b",ctr1,ctr2,ctr3,led,rst); button_1<=0; button_2<=0; null<=0; clk<=0;rst<=1; #2 button_1<=1; button_2<=0; null<=0;rst<=0; #1 button_1<=0; button_2<=0; null<=0; #2 button_1<=0; button_2<=1; null<=0; #1 button_1<=0; button_2<=0; null<=0; #2 button_1<=0; button_2<=0; null<=1; #1 button_1<=0; button_2<=0; null<=0; #2 button_1<=0; button_2<=1; null<=0; #1 button_1<=0; button_2<=0; null<=0; #2 button_1<=1; button_2<=0; null<=0; #1 button_1<=0; button_2<=0; null<=0; #2 button_1<=0; button_2<=1; null<=0; #1 button_1<=0; button_2<=0; null<=0; #2 button_1<=0; button_2<=0; null<=1; #1 button_1<=0; button_2<=0; null<=0; #2 button_1<=0; button_2<=1; null<=0; #1 button_1<=0; button_2<=0; null<=0; #2 button_1<=1; button_2<=0; null<=0; #1 $finish; end endmodule ''' i have implemented the voting machine by using simple logic so can you please remark this and check it kindly reply .🙏🙏
will this code work on xilinx vivado
I have a doubt bro...Can I do this as a project or Should I have to improve this project for my paper presentation ?
Bro, can you please help me with the verilog code for 64KX 8 Rom???