Please find the code in the link description. Any suggestions or queries are most welcomed. PLEASE SUBSCRIBE TO THE CHANNEL. LET US AIM 300 SUBSCRIBERS!!!! Other Projects- ►Traffic Light Controller in Verilog - th-cam.com/video/Yt7no6rwCVk/w-d-xo.html ►Round Robin Arbiter in Verilog - th-cam.com/video/X6oJn7r9-8s/w-d-xo.html ►Vedic Multiplier in Verilog - th-cam.com/video/6M3nyyQfpHU/w-d-xo.html ►Clock with Alarm in Verilog - th-cam.com/video/pTk1H50e8bI/w-d-xo.html ►Washing Machine in Verilog - th-cam.com/video/iAoi9jTzxcI/w-d-xo.html ►N bit Multiplier in Verilog - th-cam.com/video/lmzCdx6gkdU/w-d-xo.html ►PWM Shift Register in Verilog - th-cam.com/video/Pz9sPflKpXc/w-d-xo.html ►Vending Machine in Verilog - th-cam.com/video/tJc0blBDRzo/w-d-xo.html ►Hexadecimal Keypad Scanner in Verilog - th-cam.com/video/Y1cp2kwos5M/w-d-xo.html ►RAM - ROM Design in Verilog - th-cam.com/video/m18YU9xjETU/w-d-xo.html
how to associate that which duty cycle is attached to which bit of the 8-bit pwm...since it was defined that 0th bit should give 10% duty cycle..however it is giving 85%duty cycle..similarly 1st bit have given 20% duty cycke but same is giving 10% duty cycle.
Hi Govind, Currently we do not conduct any courses . In case you need a specific course curated for yourself. Do email/LinkedIn message me. All the best ✨
So it is basically the default FPGA in the vivado project. The default part and product family for the new project: Default Part xc7vx485tffg1157-1 Product: Virtex-7 Family: Virtex-7 Package: ffg1157 Speed Grade: -1 I do understand you are facing issues since you are a beginner. Please do mail / linkedin me so that i can send you screenshots to help you out.
Please find the code in the link description. Any suggestions or queries are most welcomed.
PLEASE SUBSCRIBE TO THE CHANNEL. LET US AIM 300 SUBSCRIBERS!!!!
Other Projects-
►Traffic Light Controller in Verilog - th-cam.com/video/Yt7no6rwCVk/w-d-xo.html
►Round Robin Arbiter in Verilog - th-cam.com/video/X6oJn7r9-8s/w-d-xo.html
►Vedic Multiplier in Verilog - th-cam.com/video/6M3nyyQfpHU/w-d-xo.html
►Clock with Alarm in Verilog - th-cam.com/video/pTk1H50e8bI/w-d-xo.html
►Washing Machine in Verilog - th-cam.com/video/iAoi9jTzxcI/w-d-xo.html
►N bit Multiplier in Verilog - th-cam.com/video/lmzCdx6gkdU/w-d-xo.html
►PWM Shift Register in Verilog - th-cam.com/video/Pz9sPflKpXc/w-d-xo.html
►Vending Machine in Verilog - th-cam.com/video/tJc0blBDRzo/w-d-xo.html
►Hexadecimal Keypad Scanner in Verilog - th-cam.com/video/Y1cp2kwos5M/w-d-xo.html
►RAM - ROM Design in Verilog - th-cam.com/video/m18YU9xjETU/w-d-xo.html
Sir I want voting machine using verilog code, can you send the link in description pls
Another awesome collab!! Very engaging and informative video. Well done😎😎💯💯💫
Thank You Yuganshi !!!
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Glad you liked it !!
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Thanks Aditya!!
Awesome presentation and delivery of the project Aditya ✨
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Thanks mumma ✨✨
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Thank you for the appreciation Yukta ✨✨
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Thanks Chirag!!
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Quite informative ✨✨
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Thanks for the appreciation Abhishek ✨
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Thanks Varun!!
how to associate that which duty cycle is attached to which bit of the 8-bit pwm...since it was defined that 0th bit should give 10% duty cycle..however it is giving 85%duty cycle..similarly 1st bit have given 20% duty cycke but same is giving 10% duty cycle.
Great work
Thank you Vankshu ✨✨
👍👍👏👏
✨😇
Bhaiyya How can i learn all this knowledge.. do u conduct any courses?
Hi Govind,
Currently we do not conduct any courses . In case you need a specific course curated for yourself. Do email/LinkedIn message me.
All the best ✨
can you please provide the code for this PWM shift register, in video it's not properly arranged.
plz apne konsa board choose kiya hai xilinx mein
So it is basically the default FPGA in the vivado project.
The default part and product family for the new project:
Default Part xc7vx485tffg1157-1
Product: Virtex-7
Family: Virtex-7
Package: ffg1157
Speed Grade: -1
I do understand you are facing issues since you are a beginner. Please do mail / linkedin me so that i can send you screenshots to help you out.
it is not a synthesizable code because you used #1 in PWM_Gen.v
Can u please provide the total code