Verilog HDL Project | Round Robin Arbiter(with code) | EDA Playground | Verilog

[@ArjunNarula1122]

Please find the code in the link description. Any suggestions or queries are most welcomed.
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[@harshitsingh480]

have you done rtl synthesis and rtl to gds flow of it? need some help of yours in layout

[@atushgoel7823]

Great work Arjun and Aditya

[@ArjunNarula1122]

Thanks ✨✨

[@yuganshibharti3892]

Explanation and presentation is phenomenal!! Awesome work guys 🔥🔥

[@ArjunNarula1122]

Glad you liked it Yuganshi !!😊

[@divanshubansal2474]

Too goood. A well explained and unique project

[@ArjunNarula1122]

Thanks Divanshu !!😊

[@PravallikaPareddy]

In testbench code it is not working for other inputs other than you have given can you please tell me that how to clear that

[@ankur6098]

did you implement the state machine..?

[@PravallikaPareddy]

@@ankur6098 how to implement that ???
Please tell me

[@ayushmahendru1858]

Amazing project guys!!

[@ArjunNarula1122]

Thanks Ayush!!

[@designerguy_13anuragsharma59]

Good going folks

[@ArjunNarula1122]

Thank you sir!

[@ishajain949]

Amazing work ✨
Great explanation of every aspect of the project Aditya✨
Great channel Arjun 💯

[@ArjunNarula1122]

Thank you for the appreciation Isha!!😊😊

[@parashgoswami7561]

Keep up the good work guys 👍🔥

[@ArjunNarula1122]

Thank you Parash!!!

[@sumantpathak7151]

Great one! Op! 🔥

[@ArjunNarula1122]

Thanks Sumant! ✨

[@sarthakwali1210]

Great and well-explained content!

[@ArjunNarula1122]

Thanks Sarthak!✨

[@tanishgarg2574]

Great explanation 🔥

[@ArjunNarula1122]

Thanks Tanish!!

[@mehakjain1956]

Great project!!✨

[@ArjunNarula1122]

Thanks Mehak!!✨

[@ritikgupta8478]

Great project !!

[@ArjunNarula1122]

Thank you Ritik!!!

[@vimminarula5523]

Nice project God bless you

[@ArjunNarula1122]

Thank you 😊😊

[@shamanthkolli2214]

Great Content , Well simplified !!!

[@ArjunNarula1122]

Thanks Shamanth ✨✨

[@varunbansal2633]

Great 🔥🔥🔥

[@ArjunNarula1122]

Thanks 😊

[@JinWonLee]

Where is the FSM code for the mask_enable signal? Is your code compilable?

[@chbhaskar6413]

Did u get the answer

[@JinWonLee]

@@chbhaskar6413 No......

[@chbhaskar6413]

@@JinWonLee i too have the same issue

[@raeleenkanda8270]

Great project ✨👏🏻

[@ArjunNarula1122]

Thank you Raeleen!!🌟

[@debasishkar761]

IN the GITHUB code I am seeing this signal is not driven "mask_enable" but used as a load.

[@runcongkuang7965]

Thanks for your wonderful explanation. However, I can't find the logic of mask_enable in the code. Do you miss that?

[@diwanshi6669]

Well done👌

[@ArjunNarula1122]

Thanks 😊

[@hassan5067]

if initially all the requests are high i.e req0 req1 req2 and req3 , only output gnt1 is getting high

[@gokulp6878]

great.can you explain i2c verilog fsm ?

[@ArjunNarula1122]

Sure Gokul, Stay tuned for more projects. I2C is definitely on the list.

[@gokulp6878]

@@ArjunNarula1122 thank you

[@Weekend_vloger_yt]

🔥🔥🔥🔥🔥🔥🔥🔥

[@ArjunNarula1122]

😇😇

[@SONAB-d3v]

from where does mask enable value come
?

[@tanujicr]

the code is missing mask_enable logic, when do you set it?

[@Jubi-to9tf]

Can we implement this project in Xilinx vivado

[@harshitsingh480]

have you done rtl synthesis and rtl to gds flow of it?

[@mehakgoyal7173]

Well explained

[@ArjunNarula1122]

Thanks Mehak!!

[@mahendrabirla5337]

Very Nice explanation can you please say where did you defined burst time
and time quantum

[@SaharshAggarwal]

Where did you drive mask_enable?

[@satishpampanaboina2409]

Sir
design of QSD Multipller Using HDL. Is my project please give me vedeo link.

[@ArjunNarula1122]

QSD multiplier is definitely on the list. Till then stay tuned!!!

[@satishpampanaboina2409]

@@ArjunNarula1122
Sir i have interview so please send me QSD multiplier using HDL video link

[@anweshangoswami5636]

Thank'a a lot for this Arjun..keep up the good work. Can you please let me about resources where I can read about the architecture of this whole design in depth..that will help for a better understanding. I searched in google, but only the scheduling algorithms are there..there isn't anything about the architecture & working anywhere!!

[@rinagharat29]

Hey...
can you please make video on round robin arbiter using xilinx vivado

[@PravallikaPareddy]

Can you implement this on FPGA?

[@somilkumar4163]

where is the code

[@ArjunNarula1122]

Verilog Code - github.com/Arjun-Narula/Round-Robin-Arbiter
Do consider Subscribing to the channel for more such videos.

[@harmanchawla33]

👍👍

[@rohandutta5694]

Good explanation but little confused on how the code works. I didn’t understand what is the driver for mask_enable. There is some part of the logic missing for that signal

[@ArjunNarula1122]

mask_enable in code is the output signal from the LASMAS state machine (refer to 7:10 in video), which gets connected to CE (Enable pin) of register. Whenever CE is active, the outputs from encoder logic gets stored in the register.
To complete the data-flow modelling for the general topology such that it justifies the circuit , it was included in code for better understanding. You can consider it as the value in ‘lgnt’ (from encoder logic) non-blockingly gets stored in lmask0 and lmask1 variables depending upon reset conditions.

[@battlizer1101]

Noice

[@ArjunNarula1122]

Thanks!!

[@chaitanyagupta6668]

nice

[@ArjunNarula1122]

Thanks!!