Please find the code in the link description. Any suggestions or queries are most welcomed. PLEASE SUBSCRIBE TO THE CHANNEL. Other Projects- ►Traffic Light Controller in Verilog - th-cam.com/video/Yt7no6rwCVk/w-d-xo.html ►Round Robin Arbiter in Verilog - th-cam.com/video/X6oJn7r9-8s/w-d-xo.html ►Vedic Multiplier in Verilog - th-cam.com/video/6M3nyyQfpHU/w-d-xo.html ►Clock with Alarm in Verilog - th-cam.com/video/pTk1H50e8bI/w-d-xo.html ►Washing Machine in Verilog - th-cam.com/video/iAoi9jTzxcI/w-d-xo.html ►N bit Multiplier in Verilog - th-cam.com/video/lmzCdx6gkdU/w-d-xo.html ►PWM Shift Register in Verilog - th-cam.com/video/Pz9sPflKpXc/w-d-xo.html
Bro in the waveform 1 means Green, 4 means Red and 2 means Yellow. How do you say that particular number indicates particular color ? Why there is number 3 ?
It is very good project and you explained in a proper manner...Thank you so much😀can you please put the video for implementation part like schematic and other things you put in the pdf please do video on it....
hello sir i have problem during running the code traffic_light_TB.v:12: error: Unable to bind wire/reg/memory `traffic_light_controller_TB' in `Traffic_Light_Controller_TB' 1 error(s) during elaboration. this showing i check many times but code is right i dont know why this showing
Hello arjun nice project well done I'm getting doubt's when I go through the PDF can u make complete video of that like schematics implemention and all
@Arjun Narula how to simulate it you have skipped the part in video can you please share how to simulate it I am unable to simulate it.please help me sir please.
Hi Arjun, I'm getting red lines corresponding to M1,S,MT,M2, and the values are xxx while Simulating. Please enlighten where things are going wrong. I'm using Xilinx ISE 7.1
Hi.. Very good explanation. If u don't mind i want a small modification for this project. I stuck at one point. Can you please solve my problem. It will be more helpful to me to understand the problem. Please
Heyy !! well the video was great and it has really helped us understand the logic but can you pls help me understand what constant/clock values to set to get the desired waveform bcoz I'm not getting the desired waveform and also what time to set in that !!!!!
1.Hi Arjun! a small query. How to differentiate whether it is mealy or moore FSM based on state diagram. In this case , it is written mealy(traffic light). Can we not make same project in mealy. How does state diagram change then. 2. reg count without initializing it to zero value, how code is running. Plz help. In testbench also it was started with rst=0
At time 07:54 when we look at the state table we can see columns of light M1 ,ME,MT and S where each of the light is represented as {RED YELLOW GREEN },for example 010 means red is off ,yellow is on and green is off. I hope this resolved your doubt. Any further questions are most welcomed .
Hello, I tried to run this code on xilinx..on spartan 6 board..with the verilog module and test bench..but I am not getting similar waveforms as the output…I am getting red waveform. Can you please help me out.
Hi Prateek, I had this project in my resume when I got an Internship at Texas Instruments, although I would strongly recommend you not to copy the project. The sole reason for uploading it was to share the knowledge I received when I learned Verilog.
Please find the code in the link description. Any suggestions or queries are most welcomed.
PLEASE SUBSCRIBE TO THE CHANNEL.
Other Projects-
►Traffic Light Controller in Verilog - th-cam.com/video/Yt7no6rwCVk/w-d-xo.html
►Round Robin Arbiter in Verilog - th-cam.com/video/X6oJn7r9-8s/w-d-xo.html
►Vedic Multiplier in Verilog - th-cam.com/video/6M3nyyQfpHU/w-d-xo.html
►Clock with Alarm in Verilog - th-cam.com/video/pTk1H50e8bI/w-d-xo.html
►Washing Machine in Verilog - th-cam.com/video/iAoi9jTzxcI/w-d-xo.html
►N bit Multiplier in Verilog - th-cam.com/video/lmzCdx6gkdU/w-d-xo.html
►PWM Shift Register in Verilog - th-cam.com/video/Pz9sPflKpXc/w-d-xo.html
Bro in the waveform 1 means Green, 4 means Red and 2 means Yellow. How do you say that particular number indicates particular color ? Why there is number 3 ?
@@bharathkrishna5917 We're taking binary values as RYG. So, for yellow it is 2's binary i.e, 010, for green 001, for red 100
@@anshumanpanigrahi7817 Perfect!
Please help to simulate the test bench
@@mounikayalla9850 Where exactly are you facing issues?
Thank you so much Arjun! I greatly appreciate your examples to ultimately understand Verilog HDL.
You're most welcomed Real E. !!! Glad I could be of some help to you!
How to simulate pls tell
Helped in my Assignment, thankyou Arjun! Well explained
Glad to be of some help , you're most welcomed Yukta!!!
How to simulate
I'm from Vietnam, thank you very much
You're welcome!!!
Amazing work ✨✨
Explanations are very nicely done!!!
Glad you liked it!
Amazing Project
and very well explained.
Thanks Atush!!!
It is very good project and you explained in a proper manner...Thank you so much😀can you please put the video for implementation part like schematic and other things you put in the pdf please do video on it....
Thank you for the appreciation Shakti ✨.
Stay tuned for the video on implementation as well.
When are you posting the implementation video ? And also the same project can be implemented on Xilinx ISE ?
Informative video, big fan sir
hello sir i have problem during running the code
traffic_light_TB.v:12: error: Unable to bind wire/reg/memory `traffic_light_controller_TB' in `Traffic_Light_Controller_TB'
1 error(s) during elaboration.
this showing i check many times but code is right i dont know why this showing
Awesome work!!
Thanks Vinayak ✨✨
Hello arjun nice project well done
I'm getting doubt's when I go through the PDF can u make complete video of that like schematics implemention and all
Thank you for your feedback Pooja ,I'll soon upload a video on implementation.
@Arjun Narula how to simulate it you have skipped the part in video can you please share how to simulate it I am unable to simulate it.please help me sir please.
tried it myself, good job
Thank you
Hey superb explanation thank you , but why there is colour initially in the waveform
Thanks!
Regarding your question I am not aware of that but will let you know as soon as I get it.
Hi Arjun, I'm getting red lines corresponding to M1,S,MT,M2, and the values are xxx while Simulating. Please enlighten where things are going wrong. I'm using Xilinx ISE 7.1
Did you find a solution to this?
@@ayushshrivastava6917 Nope bro. Did you get?
lol naah i looked a lot but couldn't find the solution. But I am almost sure the problem lies with how we have setup the project rather than the code.
@@ayushshrivastava6917 Yep, and I feel it's in the test bench code. Please let me know if you find the solution.
Same problem is occured but I am using xilinx ISE 14.5
Very informative! Thanks for this.
Hye sir..can i know what does TMG,TY,TTG and TSG stands for please??
Poi tole
Hi, these are just the variables for the time.
Hi.. Very good explanation. If u don't mind i want a small modification for this project. I stuck at one point. Can you please solve my problem. It will be more helpful to me to understand the problem. Please
I read your message on LinkedIn , let's discuss your doubts .
Arjun , how to extraxt files from github and use it in vivade? Any video on that?
We can use Sparten 6kit to implement the design
Bro I am getting high impedance as 'z' for both clk and rst. Could you please help me ?? I am using xilinx 14.2
Mee too Not getting proper output plz specify Version and Sparten which
bro can u make project in image processing in verilog
nice work man... by the way can we dump the program in spartan 3 or 3e board
I thinkit is (2:0)count vector.please clarify the doubt if i say wrong
We have taken (3:0) for count since we have 6 states the lower vector (2:0) would only have 4 states .
Super explanation
I have a doubt why should have u been taken as (3:0) vector for count.
We have taken (3:0) for count since we have 6 states the lower vector (2:0) would only have 4 states .
Amazing 👏👏
Thank you 😀
Can you explain how to simulate this in simulators?
Please refer
m.th-cam.com/video/Grs0gjeMPOY/w-d-xo.html
Heyy !! well the video was great and it has really helped us understand the logic but can you pls help me understand what constant/clock values to set to get the desired waveform bcoz I'm not getting the desired waveform and also what time to set in that !!!!!
Also how is the ps and count appearing there?
@@sanskargemawat5600 did you find any solution for this? I have the same problem.
@@anirudhmakuluri5100 Not really!!!
Can we use xilinx software for simulation?
Yes , Jatin
can you tell me how we can give coding in vivado
and what are the inputs and outputs in this projects
Regarding how to create a project and how to give inputs in vivado I'll come up with a new video.
Well done 🤩👍🏻
Thank you 😇.
can you make the same project, but in vhdl ?
Yes Alexandru-Valentin Lucan this project can be made in vhdl as well.
1.Hi Arjun! a small query. How to differentiate whether it is mealy or moore FSM based on state diagram. In this case , it is written mealy(traffic light). Can we not make same project in mealy. How does state diagram change then.
2. reg count without initializing it to zero value, how code is running. Plz help. In testbench also it was started with rst=0
Is this a standard way to design trafic control bcz i have another way to do it without this much difficulty????
Hi Ramkaran , this is not the standard way. I have formulated the problem statement in the first half of the video.
bro, I have used ISE 14.1 instead of vivado. There was no errors but the TB graph was completely different from yours. what would be the reason?
Hi Madhav , is the timescale of your graph same as the one in the video?
Input values what should we take
Bro I tried but not coming same output as in the video and in code no errors plz help me
Plz tell me step by step which board we have to select and settings how to run test bench
Not showing count and ps in output
Plz help me bro this my mini project
Plz help me
I didn't understand the state table. Where are the values when its propating from s1 to s2.
At time 07:54 when we look at the state table we can see columns of light M1 ,ME,MT and S where each of the light is represented as {RED YELLOW GREEN },for example 010 means red is off ,yellow is on and green is off. I hope this resolved your doubt. Any further questions are most welcomed .
Hello, I tried to run this code on xilinx..on spartan 6 board..with the verilog module and test bench..but I am not getting similar waveforms as the output…I am getting red waveform. Can you please help me out.
Kindly contact me on LinkedIn.
can i add this in my resume?
What is the full form of ST in state table?
Bro can I execute the code in Xilinx or Cadence tool ??
Yes , Bharath
Hi!!
I have some doubt in the state table that why you have taken 001 as green, 010 as yellow, 100 as red particularly??
its RYG, so for active green and other colours as inactive, its 001
How to simulate please tell me
Can we use a FPGA board?
Yes M SUDHANSHU we can use a Basys3 board for the project.
Bro counter and ps waveforms are not showing,please tell
I am not getting count and ps in my waveform. Can you tell me how can I get it. Nice project btw!
You might not have selected them while simulating the waveform.
@@ArjunNarula1122 How to select them?
Which fpga board have been used
The default FPGA in vivado design suite.
@@ArjunNarula1122 so how can I do in ise
when i run this code it is showing error
Hey which IEEE paper did u refer?
How to run this on EDA playground? Can you pls explain??
What does it mean for M1 M2 MT S
These are the various street lights situated on the roads. For details please refer 00:20 .
Is there FPGA present?
I am getting an error in simulation process
Please let me know the error by posting here.
@@ArjunNarula1122 I get the waveform after correcting the test bench code
Hello can please send test bench
Please help me to solve test bench
Initially there's the declaration.
Then I have toggled the reset and initialised the clock.
Where exactly are you facing issues?
Thanks for replying the problem was solved
Does this project looks good in resume for companies like TI,Qualcomm
Hi Prateek,
I had this project in my resume when I got an Internship at Texas Instruments, although I would strongly recommend you not to copy the project. The sole reason for uploading it was to share the knowledge I received when I learned Verilog.
how to simulate pls tell brother
helloo. how to implement this on hardware?
where are you writing this codee
Hi sir great explanation sir
Can u send me the documentation and ppt sir
Ur test bench is showing only one state in FPGA kit
Hello sir i get error plz help me
Hi khanoo, Can you please the error you are facing.
is there video for how to implement this using a fpga board?
How can I get it's code?
You can find the code here github.com/Arjun-Narula/Traffic-Light-Controller-using-Verilog
Do consider subscribing the channel.
Thanks dear Arjun, It's so helpful.
Hii ,I'm Ishwarya can I get the verilog code for this.
Hi Ishwarya ,you can find the code here
github.com/Arjun-Narula/Traffic-Light-Controller-using-Verilog/blob/master/Verilog%20code
Please I want butterfly structure coding vlsi
Tool name?
Objectives of this project
Bro send me pdf bro