Voting Machine in Verilog (with code) | Verilog project | XILINX | EDA Playground

[@ArjunNarula1122]

Please find the code in the link description. Any suggestions or queries are most welcomed.
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[@RahulKumar-oz2mc]

There is no link in description for code. Pls.

[@satyajeetnirmal7677]

Sir where is link for the code?

[@kavyareyya934]

There is no link for voting machine project

[@vineethshirurmath8509]

For the people like who are confused in the button control module with
if(button & counter

[@bagaspermana88]

I support this channel to produce more FPGA Projects, will appreciate it if you could do some machine learning implementation related to the project ( like Q learning) :)

[@yuganshibharti3892]

Wonderful project Harman!! 💥💥
Good work Arjun!!

[@ArjunNarula1122]

Thanks, Yuganshi!!

[@ishajain949]

Great Project and Explanation Harman ✨

[@ArjunNarula1122]

Indeed, Great job Harman!!
Thanks for watching the video Isha!!

[@abhirambhaskaran6010]

there is no code in description can you please send it

[@yuktasachdeva1204]

Waiting for this project 💥💫

[@ArjunNarula1122]

Hope you like it!

[@yuktasachdeva7822]

yes, it is amazing ✨🎉🌈

[@poojaagrawal4417]

Great job 👍 Keep progressing

[@ArjunNarula1122]

Thanks, Pooja di!!

[@diwanshi6669]

Nice project and great explanation
Keep it up guys💥💥

[@ArjunNarula1122]

Thanks Diwanshi!!

[@parashgoswami7561]

Great explanation Harman 🔥🔥

[@ArjunNarula1122]

Indeed, Great job Harman!!
Thanks for watching the video Parash!

[@Desi_Odyssey]

Mast ek dum 👌

[@ArjunNarula1122]

Thanks, didi!!

[@fevilpatel8457]

insted of this code can we use this one
""
module vm(
input clk,
input rst,
input button_1,
input button_2,
input null,
output reg led,
output reg [2:0]ctr1,
output reg [2:0]ctr2,
output reg [2:0]ctr3
);
initial begin
ctr1=0;ctr2=0;ctr3=0;
end
always @(posedge clk or negedge clk)
begin
if(rst)
begin
ctr1=0;ctr2=0;ctr3=0;
end
else
begin
if(button_1)
begin
ctr1

[@markettodayy]

Can you guys please do AES encryption using Verilog🙏🙏

[@avengers7223]

Yes would be really nice if you guys did it

[@ArjunNarula1122]

Will try to cover it in the coming videos.

[@markettodayy]

@@ArjunNarula1122 thank you so much, will be waiting!

[@arshiyagarg9882]

Nice project with great explanation 💯🌟

[@ArjunNarula1122]

Glad you liked it!!

[@akrh9177]

Thank you, sir, for providing such great and wonderful knowledge to everyone.

[@harmansaini9481]

Great work you guys!🔥

[@ArjunNarula1122]

Thanks, Harman!!

[@durgaprasadudp1476]

Can you please provide the full test bench code for this program.

[@kushagravijan7290]

Great explaination 🤩

[@ArjunNarula1122]

Glad you liked it Kushagra!!

[@ritikgupta8478]

Nice project and great explanation 💯💯

[@ArjunNarula1122]

Thank you Ritik!!

[@atushgoel7823]

Mast ek dum🔥

[@ArjunNarula1122]

Thanks, Atush!!

[@adityamehta4147]

Nice project, good going👏

[@ArjunNarula1122]

Thanks for watching Aditya!!

[@sruthipinapati5851]

Please give code in description

[@rezaulislam9176]

Thank for nice presentation . Would you make a video series about image processing with verilog coding ?

[@raeleenkanda8270]

Great one 🌟🌟

[@ArjunNarula1122]

Thanks, Raeleen!

[@DarshanAchalkar]

How I would use it in modelsim Ise simulator
Can i combine the modules in one module only

[@vaibhavgupta5339]

Thanks bro,Can you make video on implementation of router in verilog.

[@ArjunNarula1122]

Sure Vaibhav, stay tuned.

[@madhupatnana3634]

Very nice explanation....... please send code link

[@anumulaharshith5876]

Great project sir, can you plz share the code?

[@vimminarula5523]

Well done keep it up

[@ArjunNarula1122]

Thanks, Mumma!!

[@sanyamjain1617]

Good job 🔥🔥👍👍

[@ArjunNarula1122]

Thank you Sanyam!!

[@satyajeetnirmal7677]

Awesome Project ! Can you send the code in description pls

[@429sahilahammadshaik2]

I too need this code...can u plz share if available?

[@snehithreddy5576]

How to display these projects on linkdin?

[@Coco123-rl6ll]

Can we do this in xilinx vivado

[@baps24]

Can you help me to do one project in verilog on the topic ultrasound medical imaging

[@noorshaikh2549]

Sir... Can u write simple verilog code for water level indicator.. Please sir

[@anandkumar-bd2ru]

great

[@ArjunNarula1122]

Thanks!!!

[@ArjunNarula1122]

Also regarding your doubt of dot in code lines 206-219, there we are instantiating the main module (Port connection by name).

[@anandkumar-bd2ru]

thanks

[@ani_A602]

in discription code is not available provide the code

[@vishnuep6582]

damn
nice bro

[@ArjunNarula1122]

Thanks, Vishnu!!

[@saaho-m]

can u show me the rtl schematic diagram for this project

[@Coco123-rl6ll]

can you please provide the project code

[@adithyanu4830]

Will it work for spartan 6 fpga

[@pavansaikumar.m5653]

Sir,
Could you please provide SPI and I2C projects.

[@08arunc90]

I wants code for voting machine sir
Can you send me a link for this code sir

[@hashiramasenju9406]

Can u give the code in comment?

[@sreelakshmis1736]

can u plz share the code ..it is not in description

[@mumbaikaladka6718]

I need this code plz share

[@chaitanyagupta6668]

Nice

[@ArjunNarula1122]

Thanks!!

[@shrivatsaparvatikar5423]

code of voting machine?

[@Gateprep2024]

where is the code link

[@GurunadhVana-z7e]

sir please share link of the code in description

[@animeshchauhan3428]

Code???

[@Siddesh_dhurat]

Ye fpga hain kya ... Plzz reply

[@adarshpanigrahi6935]

What is dump. Vcd

[@harmanchawla33]

💥💥

[@hgameryt6151]

Cant find the code but the project is extrodonary bro

[@MasterAnime-ps3yx]

where is the code?

[@mumbaikaladka6718]

Can you share the code plz

[@varalakshmirathod3768]

please give the code bro

[@pranav_dance]

Code pls

[@virenjagwani2703]

Please post the code link

[@MichaelJohnson-tj4kx]

Source code?

[@avinsony10]

sound is very low

[@lalitsingh4-yearb.tech.ele432]

also share the code pls

[@sohamdas7775]

Voice very low

[@saibabuatmala9521]

bro how can we contact you?

[@kavya563]

Could u please send the code

[@atikpathan9693]

Code??