Washing Machine using Verilog (with code) | Verilog HDL Project by @Dhaval Gupta | FSM | Vivado

[@ArjunNarula1122]

Please find the code in the link description. Any suggestions or queries are most welcomed.
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[@daringdeshik9616]

Can u please tell us that additional code for dumping it into FPGA kit

[@vimminarula5523]

Keep it up my child

[@ArjunNarula1122]

Thanks mumma!!

[@yuganshibharti3892]

you both did phenomenal work in this collab.😎😎🔥🔥

[@ArjunNarula1122]

Thank youu Yuganshi ✨

[@Weekend_vloger_yt]

Great work ... recommended 🔥🔥🔥🔥🔥

[@ArjunNarula1122]

Thank you Anshul 😇😇

[@arunpandian294]

A request, kindly refrain from adding such loud outros. Was listening to his explanation with full sound and then had an intense sound in the ear. Pls do this. It was a great explanation btw.
Thank You

[@adityamehta4147]

Great project🔥💯
Explanation was amazing👏

[@ArjunNarula1122]

Thanks you Aditya 😊

[@ishajain949]

Great Project ✨
Informative and well explained Dhaval ✨

[@ArjunNarula1122]

Thaanks Isha!!

[@vimminarula5523]

Nice presentation God bless you my child

[@ArjunNarula1122]

Thanks mumma!!

[@akshitgupta7561]

Wow🔥🔥🔥

[@ArjunNarula1122]

Thanks Akshit!!

[@raeleenkanda8270]

Fascinating presentation 💐💐

[@ArjunNarula1122]

Thank you Raeleen 😊😊

[@saksham7111]

Nice Project and awesome explanation!

[@ArjunNarula1122]

Thanks Saksham!!

[@parashgoswami7561]

Great going Arjun 🔥🔥

[@ArjunNarula1122]

Thanks Parash!!

[@vaibhavgcool]

Great project and very well explained 👏🙌

[@ArjunNarula1122]

Thanks Vaibhav!!

[@SagarKumar-eu5xu]

Great project!
Also, the explanation was detailed

[@ArjunNarula1122]

Thank you for the appreciation Sagar ✨✨

[@yuktasachdeva7822]

Nice project and very well explained 💐💫💥

[@ArjunNarula1122]

Glad you liked it Yukta 🌟😊🎉

[@divanshubansal2474]

Wowwww🙌🙌🙌

[@ArjunNarula1122]

Thanks Divanshu!!

[@ritikgupta8478]

Awesome explanation and great project. 💯

[@ArjunNarula1122]

Thanks Ritik 😊✨

[@mehakgoyal7173]

Amazing explanation!!

[@ArjunNarula1122]

Thank you Mehak!!!

[@ayushmahendru1858]

Amazing project!!

[@ArjunNarula1122]

Thanks Ayush!!

[@InnocentGarg]

Very well presented ✨👍

[@ArjunNarula1122]

Thanks Twinkle sir ✨

[@sarthakj84]

Amazing work. Really helped a lot! Thanks!

[@ArjunNarula1122]

Thanks Sarthak!! Glad we could be some help ✨✨

[@sparshgupta3922]

Great explanation!

[@ArjunNarula1122]

Thanks Sparsh!!!

[@diwanshi6669]

Very well explained

[@ArjunNarula1122]

Thanks Diwanshi!!

[@atushgoel7823]

Great Project 🔥

[@ArjunNarula1122]

Thanks Atush!!

[@utpalsemwal6288]

Amazing work done

[@ArjunNarula1122]

Thanks Utpal!!

[@matinfazel8240]

Thanks for sharing your useful knowledge!

[@varunbansal2633]

Great work 🔥🔥

[@ArjunNarula1122]

Thanks Varun!!

[@Desi_Odyssey]

👏 bravo

[@ArjunNarula1122]

🎉

[@danishgupta4924]

Awesome

[@ArjunNarula1122]

Thanks Danish!!

[@harmanchawla33]

👍👍

[@ArjunNarula1122]

Thanks Harman!!

[@sharmaji5298]

In the "Drain water" condition to repeat itself, the "drain_valve_on" should be 1 rather than 0. Otherwise, the drain will take place just like it is on in the spin condition. Please look at 5:36 timestamp.

[@gaurav__singla]

Nice project 🔥🔥

[@ArjunNarula1122]

Thanks Gaurav!!

[@loyal8060]

keep uploading regularly

[@ArjunNarula1122]

Sure Akshay, please stay tuned for regular videos.

[@inferno3193]

Great video sir.
Sir , how many basic building blocks did we use in this?

[@ArjunNarula1122]

Thanks Inferno!!
The code itself is divided into 6 states in the finite state machine (at 1:10 ) and the testbench is also in the verilog code itself.

[@devashishbawa8236]

Great Efforts Arjun🔥

[@ArjunNarula1122]

Thanks a lot Devashish!!!

[@chiragmittal6372]

Wonderful 👍

[@ArjunNarula1122]

Thanks a lot Chirag ✨

[@sarthakwali1210]

Nice project! 👍

[@ArjunNarula1122]

Thanks Sarthak ✨

[@zanthetan8614]

Very clear explanation!
But Sir, how to do this project using hierachical design?

[@ArjunNarula1122]

Thank you!!
You could take reference from this article for hierarchical design. www.eventhelix.com/design-patterns/hierarchical-state-machine/

[@StudioSambasiva]

For the first time..
In Drain Water condition, how it can out the drain water if drain_value_on=0 (the dirty water should be present that stage only).

[@avinashbollu7603]

Can u pls provide the fsm for dialy routine (like taking states as work,sleep,eat ...)

[@ronixbhaskar8263]

Sir konsa board apne use kiya ha?? Plz urgently important hai

[@ArjunNarula1122]

So it is basically the default FPGA in the vivado project.
The default part and product family for the new project:
Default Part xc7vx485tffg1157-1
Product: Virtex-7
Family: Virtex-7
Package: ffg1157
Speed Grade: -1
I do understand you are facing issues since you are a beginner. Please do mail / linkedin me so that i can send you screenshots to help you out.

[@tarakasuryashashank1267]

please show how to implement in spartan fpga board ? how to check inputs and outputs 🙂

[@SHORTSYT-jaihind]

Did u got any answer

[@ronixbhaskar8263]

Sir board konsa use kiya hai

[@ArjunNarula1122]

So it is basically the default FPGA in the vivado project.
The default part and product family for the new project:
Default Part xc7vx485tffg1157-1
Product: Virtex-7
Family: Virtex-7
Package: ffg1157
Speed Grade: -1
I do understand you are facing issues since you are a beginner. Please do mail / linkedin me so that i can send you screenshots to help you out.

[@PrithvirajChippa]

Supurbb Brother... 💯

[@hamzagulzarjanjua7532]

how you design the state diagram of the machine, on which software

[@family-kq8ov]

Will this project run on Elbert V2 board????

[@aishahibrahim5171]

hello sir, i tried to run the verilog in quartus but its error

[@ArjunNarula1122]

Hi Aishah ,
Please do share the error here.

[@swatiyadav8724]

Will it run on vivado 2018.2???

[@adarshpanigrahi6935]

Why the motor_on is 0 after the machine starts

[@narutofan429]

Which app using

[@DileepKumar-el7fn]

Done signal is highing many times! Can u help me?

[@varunbadiger6176]

which fpga board to use to match the code

[@amankashyap2636]

Will this code run on Quartus?

[@sachintom5971]

will this code work on xilinx vivado

[@ronixbhaskar8263]

Sir testbench ka code kidar hai

[@ArjunNarula1122]

It is in the same code file .

[@prathampimpalikar8901]

Do you have the code of it

[@arunpandian294]

Also, there is an error while trying to synthesize in Xilinx ISE
always@(posedge clk or negedge reset)
begin
if(reset)
begin
current_state

[@Sandy63035]

can you please provide ppts of it

[@melissathompson1252]

I hope to see more exciting videos like this one in the near future! You should use a service such as P R O M O S M!!

[@ArjunNarula1122]

Thank you for your suggestion.

[@ashutosh2075]

Amazing work

[@ArjunNarula1122]

Thanks Ashutosh!!! Really appreciate you subscribing to the channel!!

[@parthbhatia341]

Great Explanation!

[@ArjunNarula1122]

Thanks Parth ✨