How to create a Clocked Process in VHDL

Learn how to create a clocked process in VHDL using the rising_edge() function call.
The blog post for this video:
vhdlwhiz.com/c...
The vast majority of logic in FPGA and ASIC designs use clocked logic, also referred to as synchronous logic or sequential logic. That the logic is clocked simply means that the timing of the logic is controlled by a master clock signal, not by the changing input signals.
The basic building block of clocked logic is a component called the flip-flop. Flip-flops usually have three inputs, the clock, the "data in", and the reset. It also has one output, the "data out". The way the flip-flop works is that whenever the clock signal rises from '0' to '1', the value on the "data in" will be copied to the "data out". The "data out" will remain stable until the next rising edge of the clock, or until the flip-flop receives a reset pulse.
The flip-flop implements a sample-and-hold logic. It samples the input signal on the rising (or falling) edge of the clock and holds the value steady at the output until the next clock edge.
We usually don't create flip-flop components like we did in this tutorial, but they are inferred when we create other synchronous logic by using the rising_edge() function. With the term "inferred" we mean that the during the synthesis step of the compilation, the synthesis software will recognize that the logic we have described in a process is synchronous logic. It will then map the sample-and-hold algorithm to a flip-flop in the FPGA fabric, or from the ASIC design library.

[@calin1996mh]

love you , plz don't stop making videos like this

[@VHDLwhiz]

Thank you! It's been slow lately because I've been a bit overworked. I will complete this tutorial series at least.

[@kindjupiter]

Thanks alot for this series, i hope next videos come soon.

[@VHDLwhiz]

Thanks! I'm glad you enjoyed it. It won't be long, I'm working on the next blog post and video.

[@harykishore1914]

The following is in a sequential process that's triggered by rising edge. What is output3b in decimal after 4 clock cycles. a

[@RiteshKumar-lh1xn]

You said in previous video ( signals and variables ) that the signals change after wait statements. So nRst should change after 20 ns and Input should change after 22 ns. I am a bit confused.

[@VHDLwhiz]

The signal values are updated when the program hits the Wait-statement, not when it wakes up from it. In the Signals and Variables video I didn't show the waveform, so you couldn't see this behavior.
It is a bit confusing at first, but once you understand it you will see that it all makes sense.
If you want to know more you can check out my blog post about delta cycles:
vhdlwhiz.com/delta-cycles-explained/

[@mohamed_akram1]

thank you

[@FernandoGonzalez-zw9cm]

Amazing videos, Thank you so much =D

[@mohamed_akram1]

It's strange to master VHDL and adobe products at the same time

[@VHDLwhiz]

😄😄

[@mahmutbostan6080]

hi
I do not simulate I want to lick both the rising and failing edge of the 1 entry How can I do this
I'd try
if Signal_in'event and Signal_in='1' then
i

[@En3rGyFaNforEv3r]

if the "wait" statement in VHDL doesnt work in real life, how does the "after" statement work in real life?

[@En3rGyFaNforEv3r]

ClockedProcessTB line 29

[@VHDLwhiz]

The "after" keyword also doesn't work in real life. We only use the "wait for" and "after" keywords in testbenches. They are for simulating events that are not part of the device under test. For example, in this testbench, we are using the "after" keyword on line 29 to generate the clock signal. The FPGA has to get this signal through a physical pin, but we can simulate it easily like that.

[@TheStrelok7]

write a counter

[@patapon3051]

A tip from mathematician You can also write for clockperiod = (1/clockfrequency) you will get the same.

[@VHDLwhiz]

That would be "clockperiod := 1 sec / clockfrequence" because otherwise the result won't be of type "time", and that's a compilation error.

[@patapon3051]

@@VHDLwhiz that what i meant but i wrote it as general expression. Thanks and have a nice day.

[@1972hattrick]

@@VHDLwhizi was going to ask if there was a reason to use 1000ms instead of 1s?

[@VHDLwhiz]

That would also work. It's the same.

[@1972hattrick]

@@VHDLwhiz I am going to be taking a VHDL/Verilog course at school in September. This series has really boosted my interest in the subject. Thank you for providing this resource.

[@medhm2262]

Hello haw can i make connection between two fsm ?

[@VHDLwhiz]

Then you are basically making one complicated FSM. If you insist on having the two separate FSMs, you have to invent som kind of inter-process signaling scheme to communicate between the two.

[@benjaminhodzic4840]

thank you