How to create a Finite-State Machine in VHDL
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- เผยแพร่เมื่อ 17 ก.ค. 2024
- Learn how to implement an algorithm in VHDL using a finite-state machine (FSM).
The blog post for this video:
vhdlwhiz.com/finite-state-mac...
A finite-state machines or FSM for short, is a construct whose next behavior is determined not only by the inputs, but also by its previous state.
State machines are typically used in FPGAs and ASICs to implement algorithms or protocols. As a VHDL designer it is important to understand this very important concept of digital design.
State machines can be implemented in different ways. Most common is the one-process state machine. The state of the FSM is represented by a signal with an enumerated type. The State signal is then used as selector to a Case-When statement in a clocked process.
When a predefined condition is met, the state will be changed. Thus, the FSM will enter a different branch of the Case-When statement at the next iteration of the process. - วิทยาศาสตร์และเทคโนโลยี
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as a computer science student i can't thank you enough for this
Wish had started watching your videos a while ago. I could have saved a lot of time.
Your animations are impressive. Shows that you actually put work into these videos
Thank you so much for creating such amazing videos! It's an absolute pleasure to watch them and I genuinely look forward to each new one you release. Your content is incredibly informative and I always find myself coming back to learn more from you. Thank you sincerely for sharing your knowledge and expertise with us. It's truly invaluable and greatly appreciated!
Omg I’m so thankful I found your videos, subscribed .
great video! thank you Whiz
very helpfull training !!!! thanks a lot
Brutal video!
Can I ask you a non related question about the VHDL descriptions? whether you can use them to formaly verify their correctness? with a model checker or a theorem prover for example? or is it not possible? I am going to work on the formal verification of circuits, and my advisor told me that I shouldn't use imperative HDLs like verilog and VHDL, because they only allow simulation, but from what i've found, it is possible, but since i didn't go into deep in them, I don't know how possible it is. Can you please answer me, I would apprieciate the help.
thank you very much.
Thank you so much
You're welcome!
Very nice!! how could we implement 2 sensors that check the traffic at the traffic lights?? for example, if one of the 2 streets has no cars, how would the traffic light of the other street could stay green until a car shows up??
thanks a lot!
there is a delay when counter is reaching to a certain value making the light pattern stay when it should change, in order to make light pattern change the circuit need to count 1 more to the next state, therefore the second state and so on will have 1 more counter value than it should be.
Hi I have a question. I have an FSM, but I need to go from Final state back to Idle state however, there is no information on how to go back to Idle state.
My code atm reads: when Final=>
if A='0' and B=’0’ then
current_state
The state doesn’t change from NorthNext, I copied the code from the blog post
thnkss very good video
I have noticed that nowadays most people write the output logic, logic and update state inside of one process clock, is that correctly done? If ha follow strictly the mealy machine structure , then from coming input to update the new state takes two clock cycles?
In my opinion, there's no "best" way to create a state machine. I think newbies and people with software backgrounds are more likely to use the one-process method. It's because they are used to sequential thinking. I have an article where I talk about one, two, and three process FSMs. Perhaps something for you?
vhdlwhiz.com/n-process-state-machine/
In your simulation the value of the lights(NorthRed, WestRed etc.) get changed as soon as the value of the state changes....but I think the value of the lights should change on the next clock cycle according to your code , say the current state is NorthNext after 5 sec the state will become StartNorth...but the lights for StartNorth should not get changed at the same time.... rather it should change on the next clock cycle because the case for StartNorth will be hit on the next clock cycle....
Actually I can't understand this... please explain.
Thank you.
The simulation is behaving as you are expecting, the output is lagging one clock cycle behind the State signal. I'm talking about this starting at 16:18 in the video. That's because this FSM is a Moore type state machine. The behavior you described at first is a Mealy type state machine. You can read more about Mealy and Moore type state machines in VHDL in my later blog post:
vhdlwhiz.com/n-process-state-machine/
what program did you use to create those animations?
I used Adobe Illustrator and Adobe After Effects.
Why is the counter declaration range upto (clkFrequencyHz * 60) and not to (clkFrequencyHz - 1) * 60 ?
Edit: Added the multiplication by 60 and parenthesis
That's because the "Counter
I don't get why there's a delay between the state and the values that should be on in that state. Can someone explain me why?
There isn't ! The delay is between setting the values for the current state and instructing the machine to go the next state ( I think!)
how do i add the state waveforms in test bench
In Questa or ModelSim you can simply drag them from the Objects window to the waveform. Or right-click the signals and select Add Wave. Questa/ModelSim will figure out the state names and show them in the waveform.
I hate negative reset a lot. Why do you use it? Isn't it less intuitive and ideal than just making a reset that resets at 1? Does the industry prefer negative reset? Thanks for the clarification.
The primary motivation behind negative reset is that FPGA registers get initialized to '0' by default. If you forget to connect the reset, you get a hard failure, rather than a soft error.
I think positive reset is more common, and I've started using it in my newer articles. Instead, I use a negative reset coming from the FPGA pin. Then I create a VHDL module that synchronized and inverts the reset.
Finally, I connect the positive reset coming from the reset module to the rest of the design.
why this code is not implemetig in rtl schematic view
I don't know. If you set the RTL module as the top module and assign a generic value, it should elaborate into an RTL view. Maybe you didn't assign something to the ClockFrequencyHz generic?
Can you really type that fast, or do you speed those parts of the video up?
I sped up the video so that you don't have to watch me typing slooowly. 😄 However, I felt that this video series turned out to be too quick, so my newer videos are close to natural talking speed. I still speed up the parts where I type lots of text, though.
I have added your code to ModelSim and it doesnt show up all of the signals why?
You have to select the correct instance in the SIM tab in ModelSim. Then the signal belonging to that instance will show up in the Objects window.
@@VHDLwhiz I can only see clockfrequency, state and counter but i cant see NorthRed and others in objects tab in all of the instances. Just copied the code in your website
@@msbrdmr You probably have a new version of ModelSim or Questa that optimizes away signals it thinks you're not using.
When going to Simulate->Start Simulation, click Optimization Options and select "Apply full visibility.." That should fix the problem.
Better practise is to keep register process separated from combinational logic.
There's a constant debate going on about that. Maybe you would be interested in my article about one or multiple process FSMs: vhdlwhiz.com/n-process-state-machine/
Also, check out the comment section below the article. It contains many opinions about it.
All of your videos are great however the way you speak English is very interesting. Is that how most Swedish people speak English? The reason I'm asking this is because I'd have hard time understanding your pronounciation from time to time. But at the end, it's one high-quality lectures series. Thank you.
Hello, Cagan. Yes, it's really hard to lose the accent unless you live in an English speaking country. It's like the blind leading the blind. Some Scandinavians speak with a stronger accent, and some with less. I'm probably average. Funny story coming up. I was sitting at a cafe in Bangkok last year, and a guy came in and sat down. He only spoke a few words in English to the waitor as he ordered. But it was enough for me to pinpoint him as a Southern Norwegian native (I'm Norwegian). I started speaking to him in Norwegian, and we had a nice chat.
@@VHDLwhiz That's a funny story. Good thing is, now, I perhaps will be able to point out Norwegians if I ever come across one :)
Great video, but why only 23 lessons?
I have newer courses and articles on my website: vhdlwhiz.com
If you are a beginner, you may be interested in the FPGA and VHDL Fast-Track: vhdlwhiz.com/product/course-fpga-and-vhdl-fast-track/
Or the VHDLwhiz Membership, where you get a new course or resource item every month: academy.vhdlwhiz.com/membership
You can find some of them in the VHDLwhiz Shop: vhdlwhiz.com/product-tag/training/
But others are only in the membership portal.
Speed set to 0.75, now that sounds normal