How to create a timer in VHDL
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- เผยแพร่เมื่อ 28 ส.ค. 2024
- Learn how to create a real-time clock module in VHDL that outputs the time since startup in hours, minutes, and seconds.
The blog post for this video:
vhdlwhiz.com/c...
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* Update December 2021:
The IncrementWrap procedure shown in this video doesn't work in the latest version of ModelSim/QuestaSim. I have updated the downloadable and the blog post above, but I can't update the video.
Read more about the issue here:
vhdlwhiz.com/u...
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Measuring time is done by counting clock cycles. If you know how long a clock period is, you can measure any amount of time simply by counting clock cycles.
If the clock frequency that the design is running at is 100 MHz, one second will have passed when we have counted 100 million clock periods. If we need to count minutes, we can make another counter which is incremented when 60 seconds have passed. And similarly, we can implement an hour counter which increments when 60 minutes have passed.
We can make as many cascading counters as we need to measure days, weeks, months, or years. It's really limited only by how many resources we have available in our FPGA.
It's a good idea to send the clock frequency to the module as a generic. The clock frequency can then be assigned using the generic map when the module is instantiated. This means that we can use the same module in multiple designs, regardless of which clock frequency it's running at.
* Update December 2021:
The IncrementWrap procedure shown in this video doesn't work in the latest version of ModelSim/QuestaSim.
I have updated the downloadable and the code in the blog post:
vhdlwhiz.com/using-procedure/
But I can't update the video.
Read more about the issue here:
vhdlwhiz.com/using-procedure/#comment-233831
I think this comment relates to the next video in the series (number 19). Great series... thanks.
Hi, I really like the pace and efficiency of your videos. Your 'lets not waste time' style is very much appreciated.
Thanks, that was what I was aiming for.
He is not wasting even one clock cycle. But that's called being efficient in Germany.
Great work
I have been working with vhdl for like 9 years. But I'm really enjoying the way you design with a sold concept.
Five stars
Thanks! I appreciate the comment. I'll keep the videos coming :)
Hi i'm a student and I work on graduation project and I need for help about some design can you help me
Raya Alkhashab you are welcome if you would like me help.
Here is my gmail aloutaibi@gmail.com
ahmed alotaibi Yes sure thank you
Thanks a lot man!! This was the only video that helped!!!
I'm glad you found the video helpful!
thank you! i just had a finall proyect to present and you just saved my life. very well explained. Hope to learn more thumbs up sr.
Thanks! It's great that you found my videos to be helpful. There are more learning resources on my website vhdlwhiz.com
Send me your mail
hello , Thank you soooo much sir this helped me so much English isn't even my 1st language but i understood here better than with my professors .
Thank you! English isn't my first language either, but it's the language of the internet :)
Excelente video, me ayuda demasiado cuando se me dificulta, gracias por existir
This video was really well done. Thank you!
Hello Sir, thank you for nice serie and eagerly waiting for new topics like FSM with VHDL.
thank you very much
Hello, how would I show the timer on the LCD of the fpga spartan 3A
I've written about how to display numbers on a 7-segment LCD here: vhdlwhiz.com/dual-7-segment-display/
Hi Sir, i'm a total vhdl novice and i've a silly question. The Seconds signal became 0 after 0.1 simulation seconds (100000000 ns) and this is ok because this is the time needed to take the DUT out of the reset. But, as you see at 10:19 , the Seconds signal increments to 1 at 1.2 simulation seconds (1200000000 ns). I don't understant why it seems to lose another 0.1 second. I've tried your code on Modelsim and each time the Seconds signal seems to be incremented every 1.1 real seconds. I'm sure that it is ok but can you explain me why? Thank you for your videos. I'm a university student and i'm currently studying for the fpga programming exam.
Dear Whiz, in T18_Timer.vhd, I added 'ticks' to the port and removed it from the architecture. Then in T18_TimerTb.vhd I added 'ticks' to the architecture and the port map.
This worked.
So my question is, what is the difference between your program and mine? What did I just do? In other words, in T18_Timer.vhd what is the difference between signals defined under entity and those under architecture?
Thanks.
The entity is just a way to pass signals between modules. If you defined the Ticks signal in the testbench and passed it to the module as an inout mode signal, there would be no functional difference.
However, we can limit who can update signals by using "in" and "out" modes on entities instead of "inout" as we did in this example. Modes "in" and "out" are by far more common.
@@VHDLwhiz Thanks a lot. As you can see, I am following all your lessons :)
Hi I am a beginner in VHDL and I have a question, is there a reason why you use a negative reset instead of a positive? Or is it just a matter of your taste?
I liked to use negative reset because most FPGAs will initialize signals to '0' by default. If you forget to actively control the reset, it's going to fail brutally rather than work silently. I've stopped using negative reset in my newer tutorials because it's confusing. Positive or negative doesn't really matter.
@@VHDLwhiz I am trying to make an led blink 3 times after a short press of the button and then it must stop blinkin if the button is not pressed anymore. I have already managed to make the led keep blinking while the button is pressed and stop when the button is released but I cannot figure out how to make it blink only 3 times after a short press. I guess it is not a hard task to do. And I am willing to learn! Unfortunately my university is a waste of time, some professors just hardly want to explain anything and if you ask them a question they look at you as if you have commited a crime so I am watching your playlist trying to figure out how to do it. Still no idea. Could you guide me through give some advice? It is already 3 week and I am getting hopeless.
@@hekk_tech5975 Hello. You can make a finite-state machine that controls the counting. For example, with the three states: RELEASED, PRESSED_COUNTING, PRESSED_IDLE. There are many ways to design the state machine with other states as well. Read about state machines here: vhdlwhiz.com/finite-state-machine/
You can join my Facebook group to ask questions like yours: facebook.com/groups/vhdlwhiz/
@@VHDLwhiz nice, thanks for the answer! Yes I joined the group too. I will try to create a FSM with help of your tutorial.
I can see that whenever you run a code that has an error, it will appear in the transcript and I would like to know how to make it appear because whenever I compile my project it only shows "Compile of "file name" failed with 2 errors" but not the line where the error occurs. Thanks!
Select the Project tab in ModelSim. Right-click on a blank space in the project window, not on a file name. Select Project Settings. Check the box titled "Display compiler output" and hit OK.
Hey great work, how can I display the output on 7 segment displays now ?
Hi Adrian, I answered your question in the comment section on my blog: vhdlwhiz.com/create-timer/#comment-26126
compilation error - it says it can't have 2 wait until statements in a process if, I delete one & proceed again it says wait statement must-have condition clause with wait until
I'm guessing you are trying to synthesize the process. That doesn't work because there's no hardware in the FPGA that can realize what you are asking with the VHDL code. In code meant for synthesis, we need to follow some rules to stay within what's physically possible. But in testbenches, you can play around to the full extent of the VHDL language. Try to compile the example in a simulator like ModelSim. 🙂
@@VHDLwhiz yes, I tried in modelsim altera, it says work library doesn't exist. How to add work library to modelsim altera?
@@harykishore1914 "work" is the default library name in ModelSim. You can create it by typing "vlib work" in the ModelSim console.
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 22.12.2023 20:38:19
-- Design Name:
-- Module Name: timer - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity timer is
-- Port ( );
port(
rst : in std_logic;
clk : in std_logic;
hours_out : out integer;
minutes_out : out integer;
seconds_out : out integer;
);
end timer;
architecture Behavioral of timer is
signal ticks : integer := 0;
signal clk_f : integer := 50000000;
signal hours, minutes, seconds : integer := 0;
begin
process(clk)
begin
if rst = '1' then
ticks