How to use Port Map instantiation in VHDL

Learn how to create a VHDL module and how to instantiate it in a testbench. The port map is used for connecting the inputs and outputs from a module to local signals ion the design where it’s instantiated.
The blog post for this video:
vhdlwhiz.com/port-map/
A module in VHDL is a self-contained design unit which communicates with the outside world through a set of input and output signals. The code which defines the inputs and outputs for a module is called the “entity”.
Visit the blog post to view the syntax for declaring an entity port and for instantiating it using the port map statement.

[@AhmadAsmndr]

Thank you very much. Very helpful Video!

[@Niko_Leben]

Great video!

[@TheStrelok7]

PERFECT!!!

[@broytingaravsol]

why can't the defined entity content built in the same console for port map?

[@iloveukraine-subscribe1kgo822]

I understood your code.. i was referring ur example with another one in my university lab. Here they have written port declaration under architecture, but again they have written signal inputs with the same name. It is really needed to write port in testbench or signal is enough?
And u didn't write port declaration under your tb. Thats y I got this question.
ARCHITECTURE behavior OF wb_switch_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT wb_switch
GENERIC (
memaddr : generic_addr_type := CFG_BADR_LED;
addrmask : generic_mask_type := CFG_MADR_LED
);
PORT(
clk : IN std_logic;
rst : IN std_logic;
btn : IN std_logic_vector(6 downto 0);
sw : IN std_logic_vector(7 downto 0);
wslvi : IN wb_slv_in_type;
wslvo : OUT wb_slv_out_type
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal rst : std_logic := '0';
signal btn : std_logic_vector(6 downto 0) := (others => '0');
signal sw : std_logic_vector(7 downto 0) := (others => '0');
signal wslvi : wb_slv_in_type;
signal slvi : wb_mst_out_type;
signal slave_out_data: std_logic_vector(31 downto 0) := (others => '0');
--Outputs
signal wslvo : wb_slv_out_type;

[@AlexanderForsman]

If i wanted the inverted output on the instansiated version, how would i do that?

[@VHDLwhiz]

You can make a new signal with a concurrent assignment like this:
InvertedSig

[@AlexanderForsman]

@@VHDLwhiz i tried it, but the compiler complained that I couldn't use an output signal like that.

[@vhdlwhiz2]

@@AlexanderForsman Oh, OK. If you want to read an output within the module, you must create a new "shadow" copy of it which you use consistently within the module. Just a regular signal which you can read and drive. Then you assign to the output concurrently from the copy like this:
MyOutput

[@AlexanderForsman]

@@vhdlwhiz2 ok, thx. I'll try that.

[@zattiya]

you /should have picked a more complicated example to show such a basic concept.

[@huseyinsenol1769]

LMAO