How to use the most common VHDL type: std_logic

Learn how to create a signal of type std_logic in VHDL. A std_logic signal models the value that a can be carried by a single wire in a digital logic circuit.
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To use the std_logic type, this IEEE library must be imported at the top of the .vhd file:
library ieee;
use ieee.std_logic_1164.all;
The syntax to declare a signal of type std_logic:
signal signal_name : std_logic := [intial_value];
The initial value may omitted. The default initial value is 'U', which means "uninitialized".
A signal or variable of the std_logic type can have any of the following values:
'1' - Binary 1
'0' - Binary 0
'U' - Uninitialized
'X' - Unknown / multiple drivers
'Z' - High impedance / no driver
'H' - Weak 1 / pullup
'L' - Weak 0 / pulldown
'W' - Weak signal, can't tell if 1 or 0
'-' - Don't care (used in comparisons)
Normally we only use the values '1' or '0' to model a bit value. When 'X' or 'U' appear, its usually because of some kind of error. The other meta-values are mostly used for modelling external interfaces.
The std_logic is a resolved type. What this means is that if we try to drive differing values onto the same signal from two or more processes, the value will be determined by a "resolution table". This means that the program won't crash, but the signal might get a different value than any of the drivers are applying to it. The most common meta-value is 'X'.

[@XDbiggy]

Your compilation errors are an extremely good strategy for making your viewers learn and retain info. I like it!

[@VHDLwhiz]

Thanks! Then I will do more of that when it's applicable.

[@angeloperez1136]

Thanks! I've already made the signals appear in the 'Objects' by just unchecking 'Enable Optimization' before the simulation.

[@parkerd2154]

Keep the great videos coming. You're really helping a lot of people and you deserve more subs

[@VHDLwhiz]

Thank you! Good to hear that you are finding them useful. I am actually rendering a new video about finite-state machines right now.

[@parkerd2154]

excellent!

[@Ma1ne2]

Amazing tutorial series to far! I am having a lot of fun a learning great new stuff!

[@marcomoldenhauer7903]

The explanation is very clear! Thank you very much!

[@unguder]

For the ones who cannot see signals in the "object" window, after clicking the "enable optimization" enter the "optimization options" in "start simulation" window. Then choose " Apply full visibility to all modules"

[@Formula_myan]

bro u are a wizard i'm a masters student and i choose vhdl but idk have the coding knowledge i had the background of doing it in CRO (cathode ray osciloscope) i was struggling to do my assignments now i can rely on ur playlist

[@ryledesirabelli4151]

how do you declare std_logic in the entity ?

[@mati3me]

well explained

[@mazenezzeddine8319]

Thanks. In driver B, why signal 2 and 3 assignments are affected despite there is no wait statements?

[@valerioantoniovicidomini6498]

second process has a sensitivity list, it wont start again if Signal1 doesn't change.

[@sakuranooka]

@@valerioantoniovicidomini6498 You mean, "third" process, right?

[@sakuranooka]

The second process doesn't have a sensitivity list, but still seems to be executed in each iteration. How come?

[@atlaskaiser9951]

Check the Dataflow, in simulation right-click on your file name, and select 'add Dataflow'.

[@greggkulcak6348]

In ModelSim my waves are always displayed at an offset of 100ns, so 0-100 is blank and then my signals start showing at the 100ns point. Is there any way to fix this in the settings?

[@VHDLwhiz]

If you run the simulation for 100 ns without opening the waveform and then add the signals to the waveform, then you may see that the first 100 ns are blank. That's because their values haven't been recorded until you added the signals to the waveform at 100 ns.
Try to type "restart; run 100 ns" after adding the signals, but without closing the waveform. It should record the values from 0 ns on that second run.

[@greggkulcak6348]

@@VHDLwhiz Yes it looks like that was the issue I was causing, thanks for the reply!

[@gustavosousa4363]

what to do when it gives you an error? " std_logic does not match with a string literal"

[@VHDLwhiz]

Perhaps you used double quotes "1" instead of single quotes '1'?

[@atlaskaiser9951]

try capital 'Z' instead of 'z'.

[@Gian95R]

Could you please give us some exercise?

[@VHDLwhiz]

You can try one of the VHDL code quizes at vhdlwhiz.com/basic-vhdl-tutorials/

[@luthfymuhammad788]

why doesn't my signal appear in "object". is there a solution for this?

[@VHDLwhiz]

Probably because you have selected a different instance in the "Sim" tab. Click around in the Sim tab to the left of the ModelSim window, and you will see other signals appear in the Objects window.