Thanks so much for this! I've spent almost two weeks failing to do clock recovery on an NRZI signal using a CD4046 PLL chip. I just couldn't figure out why it loses lock as soon as any zeroes appear in the data stream. Analog is not my forte and I had a horrible time working with the 4046. I decided to try a digital solution and your Arduino method works flawlessly for NRZI with some small modifications. Absolutely brilliant!
Thank you so much, I have watched several videos to find out what a clock recovery is but didn't get any clue, and now I can find it out. Although I know nothing about electronics, your explanation makes it easy to understand. Thanks again.
Great video 👌.I think you should advertise your channel in the bigger electronics channels because you deserve more subscribers and Electronics engineers out there are missing great stuff.
Interesting introduction and explanation of the digital PLL with the NCO. Instantly reminded me of the horizontal sync mechanism in old TVs, where sampling the horizontal deflection ramp by the sync pulse generated the error voltage for the horizontal oscillator. Pretty sure the digital PLL is the same idea. Great videos, great channel!
great video, the best I have seen so far explaining the phase detector and bit recovery clock. You could implement the pulse edge detector in software by attaching two interrupts (a rising edge and a falling edge interrupt routine) performing the phase sensing.
That’s a good one, essentially the use of low bandwidth PLL is equivalent to using a very high Q (Q>> no. of consecutive bits) band pass filter after the edge detector. Using such a band pass filter too, will help recover the clock.
Thanks for the video! With all the visualizations and hands on it was way easier to understand! After this video the slides of my prof make way more sense haha
Excellent video ! I have a question, why did you choose 9° as the phase lock target ? I understand that this allows the data signal to settle before taking a reading, but by that logic why not choose 180° so that the reading falls right "in the middle", furthest away from the rising and potential falling edge ? Thank you !
Nice one again! Maybe another step could be to use the recovered clock and persistence on the data trace to make this into an eye diagram and check the quality of your data line 😀
Very nice, my previous experience with clock recovery was mostly that it is a pain in the butt. I had to implement it in a FPGA for my Master thesis, where I didn't really have a spare PLL. I built a similar approach though, since the bitrate was known but could have some tolerance, I started with an edge detector, and counted the time between the pulses, I then took the minimum time and averaged it. I then took this to correct the expected bitrate. I works fine, however when there are VERY long bitstreams of only 1s or only 0s, it gets pretty inaccurate. To prevent this, very long pulse times get sorted out. This turned out to be very stable.
Nice!! I have used that technique I called feedforward clock sync. This technique also happened me when I made tesla coils, using a FPGA you can compensate the on/off delays of the IGBTs. It is safer because a closed loop pll could destabilize killing the power bridge !
Good one. Thank you for creating the video. Take a lot of effort - with lab setup etc. It is highly appreciated. My brain is 10 lbs heavier after this video - the burden of knowledge. :)
Hallo! Habe ich da am Anfang "...and in DIESEM Video" gehört? Aufgrund deiner Aussprache hab ich immer angenommen, dass deine Muttersprache Englisch ist, stimmt das gar nicht? Wo wohnst du?
Great explanation of the digital PLL. I'm just a simple hobbyist. I'm trying to recover a clock from an analog carrier signaling digital data via phase shift keying. I was curious. How could you recover a clock from that? It seems like edge detection is a different beast in this regard. I think delaying the signal and doing math on the samples is still applicable, but obviously XOR won't work. I tried simply dividing and that generate pulses on phase(edge) transition... but only if my delay signal was at a specific phase relationship to the realtime signal. Is this the wrong approach altogether?
I have a video showing a squsting loop bpsk detector. Take a look. It is basically a PLL over the signal squared. Squaring removes phase information, pll locks to that and its output is a stable reference to further decode the bit stream
I would like to ask you a question. Can a crystal filter "coulour" the output frequence due to the crystals oscilation? For example: imput 10mhz and get a frequency out that dont correspond exactly with the input frequency due to the crystals in the filter?
I'm CSE student, and trying to understand this PLL thing. Guys at 7:35 , "If we have bit rate of 1200 bits ...pulse will be of 1200 Hz.." My Question is : once we detected edges/pulse of input signal (which will have different widths/distance between pulses dependent on data for example 110001, so the pulse would be like **|***| (*=diff volt representing bits 1 or 0 , edges=|), right?) , how do we get correct clock? . Also (7:35) why pulse repetition rate would also be 1200 Hz, which is dependent on data bits. for examples a data like 1001111100110 wouldn't have edges/pulse of same interval. would it?
Great video have a question though..it might be long but bare with me.. to my understanding in ethernet UTP 100mbps we use 4b/5b coding with NRZI to increase the number of transitions (edges) so we don't loose the phase lock of the clock.. in fiber though we are using NRZ not NRZI so multiple 1s or multiple 0s in data can cause loosing the clock synch due to edges absence.. how this is solved in fiber ?
Thanks man! I don't know the exact case of fiber.. A common technique is called bitstuffing It is very simple: we force a transition when we have a long stream of zeros or ones. USB uses this technique. For example, we can add a transition always we have more tha 5 zeros/ones 000000000 -> 0000010000 The receiver knows this and ignores the bits inserted
I have a question. From spectrum of the NRZ encoded signal, we can find that the bit rate is 1200Hz because the notch happens in 1200Hz. From 1200Hz, it's enough to get CLK. However, why do you still want to get 1200 from Spectrum of signal edges?
@@AllElectronicsChannel You means that from the notch we can get 1200Hz，but not the phase of CLK, so we still need to get signal and spectrum of the signal edge from which we can get the phase by PLL?
Even more than that.. you are seeing the notch because you are a human... but there is not energy there, there is no way to "capture" the notch.. to "measure" the notch. When we detect the edges we are generating energy at 1200Hz. Energy that we can measure with the PLL, lock on it...
@@AllElectronicsChannel Thanks so much! I totally understand my question. Really thanks, the funny thing is that my none of my teacher have ever taught me that and I always feel confused about the basic concept. Thanks!
Hi, thanks for the video, watching for the second time. I have a question, could this setup work using SFP, CPRI and optic fibre? Thanks once more in advance.
@@AllElectronicsChannel Can you prepare a course on that, from basics to advanced, I am interested in that (if affordable or free), I want to capture the entire workflow. Thanks
Beautifully Explained, fantastic work sir. I will be regularly following the channel for videos and spread the good word too. Keep up the good work. By the way which is the preferred method to support the channel via patreon or YT super thanks, I have heard that YT takes a cut at its end
Excellent video! I was able to implement in arduino and then on FPGA since actually for a 9600 baud rate, an arduino running at 8MHz may actually only get a signaling rate of like 40KHz since here you have to implement the NCO in software and the phase alignment logic. That's as fast as my main loop would run at least, so there's basically no fine control over the phase to be 9 degrees lol. My recovered clock WAS shifted properly for reading the UART but I believe the phase is entirely due to the mentioned slowness. It happens to make a good phase angle for the data signal to stabilize at 9.6KHz... but I wanna do faster shit like USB next. Oh also, yeah I did this on my FPGA too, and the difference was that it locked on 100% to the edges pretty much perfectly as soon as I could just get the verilog to compile. That's the difference from 100MHz and like (in the range of) 100KHz
Forgive my dumbness, I was always confused by clocks and still am. Have a question: So If I for example. continuously have data 00110011... and PLL is locked thinking clock is actually 2x slower - and now I get data 01 - it won't be recovered correctly? Or did I get everything completely wrong?
@AllElectronicsChannel I think my question isn't very clear. Apologies for that. Please see that at 4:53 the spectrum shows dips (notch) at regular intervals at the baud rate. What causes these dips to appear (become visible) in the spectrum?
It is a direct result of the phenomena of spectrum domain. The Fourrier transform of a pulse with finite width is a sin x/x with notches at the main frequency.
Hey! Bro! It's a great video and really appreciate your effort. I'm looking into your arduino code but it's not that easy to match your code with the diagram. Could you add some comments on the arduino code and some math equations for the diagram. Thanks Bro again!!
@@AllElectronicsChannel Thanks for quick reply! I manage to understand most of the code except for one thing, "delay equalizer", can you elaborate on that part? What if i remove the code?
@@nova0302 Nice!! The "delay equalize" is a trick used to make the run time of code be the same for different branches. In this way, we have less jitter on the overall loop, because different paths of the code will need more/less time to execute. So probably I added the "delay equalizer" in a fast section of the code, to make the execution time of that branch more even in respect to other branches of code
@@AllElectronicsChannel Sorry, can't find a way to contact with you, but really like your videoes, and could you help to confirm, if I can post your video on my channel, to spread your great energy?
baud rate is the same as symbol rate and should be in symbols/sec instead of bits/sec...some information can be misleading, so I tend to take it with a grain of salt...
Support the channel becoming a Patreon: patreon.com/allelectronics
I am a brazilian electronic tecnician. I have learned Telecom in yours electronic YOU TUBE Channel. THANK you my dear teacher Greg!!!!!😎😎😎
great video. i have been waiting for this for months. it sheds me the light. crystal clear. thank you.
Thanks so much for this! I've spent almost two weeks failing to do clock recovery on an NRZI signal using a CD4046 PLL chip. I just couldn't figure out why it loses lock as soon as any zeroes appear in the data stream. Analog is not my forte and I had a horrible time working with the 4046. I decided to try a digital solution and your Arduino method works flawlessly for NRZI with some small modifications. Absolutely brilliant!
Amazing!
A great hand-on demonstration and explanation of the background theory! Thank yuo so much!
Thank you so much, I have watched several videos to find out what a clock recovery is but didn't get any clue, and now I can find it out. Although I know nothing about electronics, your explanation makes it easy to understand. Thanks again.
I had always wondered how this was accomplished. Thank you for making a video about it! Very informative, and the paper is excellent.
Thank you!!
The best channel of analog and digital signal ever.
Thank you!
Great video 👌.I think you should advertise your channel in the bigger electronics channels because you deserve more subscribers and Electronics engineers out there are missing great stuff.
Thanks! The best way is you helping me spreading the content !
Thank you for the clear explanation
Interesting introduction and explanation of the digital PLL with the NCO. Instantly reminded me of the horizontal sync mechanism in old TVs, where sampling the horizontal deflection ramp by the sync pulse generated the error voltage for the horizontal oscillator. Pretty sure the digital PLL is the same idea. Great videos, great channel!
Really nice, I didn’t know that old TVs used this technique. Thanks!
great video, the best I have seen so far explaining the phase detector and bit recovery clock. You could implement the pulse edge detector in software by attaching two interrupts (a rising edge and a falling edge interrupt routine) performing the phase sensing.
awesome video. I’s been wanting to understand this exact process for months
Glad you enjoyed it!
Excellent video, crystal clear understanding.. thank you for putting this together,
Glad you enjoyed it!
Awesome video! You are a great engineer and a brilliant communicator. Keep it up!
Thank you very much!
That’s a good one, essentially the use of low bandwidth PLL is equivalent to using a very high Q (Q>> no. of consecutive bits) band pass filter after the edge detector. Using such a band pass filter too, will help recover the clock.
Exactly!
Thanks for the video! With all the visualizations and hands on it was way easier to understand! After this video the slides of my prof make way more sense haha
Hahaha welcome!
EXCELLENT explanation!
Excellent video !
I have a question, why did you choose 9° as the phase lock target ? I understand that this allows the data signal to settle before taking a reading, but by that logic why not choose 180° so that the reading falls right "in the middle", furthest away from the rising and potential falling edge ?
Thank you !
There not a reason.. I only chose 90 deg.
90deg is also a common phase of equilibrium in hardware PLL, when using the XOR phase detector
I want to thank you for your videos!, I Have thanks to them built a VCO and bought to many frequency counters :). Thanks for the inspiration!!
Hahahahahah!!
Incredible explanation-thank you so much for this!
Thanks my friend!+
Thank you so much for this great video, you have explained this topic very well.
Thanks !!
Very clear explanation. Thank you.
Thanks!
Nice one again! Maybe another step could be to use the recovered clock and persistence on the data trace to make this into an eye diagram and check the quality of your data line 😀
😏😏😏🤫🤫
Very nice, my previous experience with clock recovery was mostly that it is a pain in the butt.
I had to implement it in a FPGA for my Master thesis, where I didn't really have a spare PLL.
I built a similar approach though, since the bitrate was known but could have some tolerance, I started with an edge detector, and counted the time between the pulses, I then took the minimum time and averaged it. I then took this to correct the expected bitrate. I works fine, however when there are VERY long bitstreams of only 1s or only 0s, it gets pretty inaccurate.
To prevent this, very long pulse times get sorted out. This turned out to be very stable.
Nice!! I have used that technique I called feedforward clock sync.
This technique also happened me when I made tesla coils, using a FPGA you can compensate the on/off delays of the IGBTs. It is safer because a closed loop pll could destabilize killing the power bridge !
Aren’t long sections of 0’s/1’s avoided by using special coding schemes that create a more balanced bitstream?
Yes !
Good one. Thank you for creating the video. Take a lot of effort - with lab setup etc. It is highly appreciated. My brain is 10 lbs heavier after this video - the burden of knowledge. :)
Haahahahha
That was amazing.
🙏🏼🙏🏼
Thank you! That video was great!
Glad you liked it!
Very interesting and well explained. Thanks.
Thanks!
Hallo! Habe ich da am Anfang "...and in DIESEM Video" gehört? Aufgrund deiner Aussprache hab ich immer angenommen, dass deine Muttersprache Englisch ist, stimmt das gar nicht? Wo wohnst du?
No!
Thank you for making this video...tnx man
Great explanation of the digital PLL. I'm just a simple hobbyist. I'm trying to recover a clock from an analog carrier signaling digital data via phase shift keying. I was curious. How could you recover a clock from that? It seems like edge detection is a different beast in this regard. I think delaying the signal and doing math on the samples is still applicable, but obviously XOR won't work. I tried simply dividing and that generate pulses on phase(edge) transition... but only if my delay signal was at a specific phase relationship to the realtime signal. Is this the wrong approach altogether?
I have a video showing a squsting loop bpsk detector. Take a look. It is basically a PLL over the signal squared. Squaring removes phase information, pll locks to that and its output is a stable reference to further decode the bit stream
Tardé 2 ns en saber que eran 90 grados y no 9 jaj. Muy buen video. Nice english too! Salut!
😁😁
quick question. what are the consequence if you oversampling it even shifting the sync signal with 90 degree? like would the detector go on the edge?
Hi, I did not get. For the digital version I demonstrated, the system is running oversampled.
At the FFT waveform, there were peaks at 1.2KHz, 2.4, and 3.6. Why does 2.4 and 3.6KHz come from?
The frequency components of time domain pulses are also "peaks" in frequency, spaced by the 1 / T, where T is the repetition period of the pulse.
excellent explanation
Glad you liked it!
Nice, quite useful to know of NCO, i think it can be used to used to implement a digital PLL for a grid connected inverter..
It is a perfect use! Replace the edge detector with a zero crossing detector and voala!
I would like to ask you a question. Can a crystal filter "coulour" the output frequence due to the crystals oscilation? For example: imput 10mhz and get a frequency out that dont correspond exactly with the input frequency due to the crystals in the filter?
I'm CSE student, and trying to understand this PLL thing. Guys at 7:35 , "If we have bit rate of 1200 bits ...pulse will be of 1200 Hz.." My Question is :
once we detected edges/pulse of input signal
(which will have different widths/distance between pulses dependent on data for example 110001, so the pulse would be like **|***| (*=diff volt representing bits 1 or 0 , edges=|), right?) ,
how do we get correct clock? . Also (7:35) why pulse repetition rate would also be 1200 Hz, which is dependent on data bits. for examples a data like 1001111100110 wouldn't have edges/pulse of same interval. would it?
@AllElectronicsChannel plsss help me understanding it
one the rare video _ thanks for sharing
Glad you enjoyed it
Great video have a question though..it might be long but bare with me.. to my understanding in ethernet UTP 100mbps we use 4b/5b coding with NRZI to increase the number of transitions (edges) so we don't loose the phase lock of the clock.. in fiber though we are using NRZ not NRZI so multiple 1s or multiple 0s in data can cause loosing the clock synch due to edges absence.. how this is solved in fiber ?
Thanks man!
I don't know the exact case of fiber.. A common technique is called bitstuffing
It is very simple: we force a transition when we have a long stream of zeros or ones.
USB uses this technique. For example, we can add a transition always we have more tha 5 zeros/ones
000000000 -> 0000010000
The receiver knows this and ignores the bits inserted
@@AllElectronicsChannel
I think this is the correct answer ..thanks again for the great video
This is awesome. Thank you!
🙏🙏🙏
I have a question. From spectrum of the NRZ encoded signal, we can find that the bit rate is 1200Hz because the notch happens in 1200Hz. From 1200Hz, it's enough to get CLK. However, why do you still want to get 1200 from Spectrum of signal edges?
Hi! You need information at 1200Hz to recover the phase of the clock. Seeing the notch is notch exactly knowing the phase!
@@AllElectronicsChannel You means that from the notch we can get 1200Hz，but not the phase of CLK, so we still need to get signal and spectrum of the signal edge from which we can get the phase by PLL?
Even more than that.. you are seeing the notch because you are a human... but there is not energy there, there is no way to "capture" the notch.. to "measure" the notch.
When we detect the edges we are generating energy at 1200Hz. Energy that we can measure with the PLL, lock on it...
@@AllElectronicsChannel Thanks so much! I totally understand my question. Really thanks, the funny thing is that my none of my teacher have ever taught me that and I always feel confused about the basic concept. Thanks!
Hi could you explain: the two characters ? : in the following syntax why are they there PORTB = (nco) ? (PORTB | (1
Search for Ternary operator
@@AllElectronicsChannel thank you for your prompt reply.
Hi, thanks for the video, watching for the second time. I have a question, could this setup work using SFP, CPRI and optic fibre? Thanks once more in advance.
Of course! It is used
@@AllElectronicsChannel Can you prepare a course on that, from basics to advanced, I am interested in that (if affordable or free), I want to capture the entire workflow. Thanks
Beautifully Explained, fantastic work sir. I will be regularly following the channel for videos and spread the good word too. Keep up the good work. By the way which is the preferred method to support the channel via patreon or YT super thanks, I have heard that YT takes a cut at its end
Thank you so much! I think patreon is nice platform.
Gregory! Sabe muito!!!!!
Excellent video! I was able to implement in arduino and then on FPGA since actually for a 9600 baud rate, an arduino running at 8MHz may actually only get a signaling rate of like 40KHz since here you have to implement the NCO in software and the phase alignment logic. That's as fast as my main loop would run at least, so there's basically no fine control over the phase to be 9 degrees lol. My recovered clock WAS shifted properly for reading the UART but I believe the phase is entirely due to the mentioned slowness. It happens to make a good phase angle for the data signal to stabilize at 9.6KHz... but I wanna do faster shit like USB next.
Oh also, yeah I did this on my FPGA too, and the difference was that it locked on 100% to the edges pretty much perfectly as soon as I could just get the verilog to compile. That's the difference from 100MHz and like (in the range of) 100KHz
Great!!
선생님 감사합니다
What happens when continuous 1's or continuous 0's are sent ?
You lose sync after some time.
Hello, how should the PLL design change when the frequency of the NRZ data is variable (varying for example from 40Khz to 640Khz)/
You need to vary the center frequency of the NCO to match the data rate.. So the PLL makes smalls adjusts to align the NCO.
@@AllElectronicsChannel Thanks a lot. That's what I was thinking.
Forgive my dumbness, I was always confused by clocks and still am. Have a question:
So If I for example. continuously have data 00110011... and PLL is locked thinking clock is actually 2x slower - and now I get data 01 - it won't be recovered correctly? Or did I get everything completely wrong?
Ok I think I found online that training sequence and type of encoding where each bit is represented by transition is what helps this?
Yes! And also: the PLL will not think the clock is 50% lower... The PLL is designed to correct for deviations.. like 5 ppm (100 * 5 / 1000000) %
Thank you so much
Thanks
12:17 9°? Maybe you mean "ninety" degrees? Anyway, very nice presentation. Thank you very much.
90! hehe
I dont understand when you say pulse repeatation rate will also be 1200HZ?? How can it be ?
What exactly you didn't get?
Same
Cool. Well explained
Thanks!
Super awesome!
Thank you! Cheers!
Why is the baud rate edge visible?
hum, I did not understand the questio, hehe
@AllElectronicsChannel I think my question isn't very clear. Apologies for that. Please see that at 4:53 the spectrum shows dips (notch) at regular intervals at the baud rate. What causes these dips to appear (become visible) in the spectrum?
It is a direct result of the phenomena of spectrum domain. The Fourrier transform of a pulse with finite width is a sin x/x with notches at the main frequency.
@@AllElectronicsChannel That explains it well. Thanks ❤️
I love your stuff
Thanks man!
Please help me I'm rf equipment repair work my requirement 22 ghz spectrum analyzer any old used
Im not seeing how this works with oscillating or non constant clock frequencies. Very interesting though
Frequency tracking depends on the loop order!
That’s nuts!
Thanks man!!
Hey! Bro! It's a great video and really appreciate your effort.
I'm looking into your arduino code but it's not that easy to match your code with the diagram.
Could you add some comments on the arduino code and some math equations for the diagram.
Thanks Bro again!!
Hi man, thanks! The code have many layers of tricks/simplifications... Which parts you want to understand better? I can help you here
@@AllElectronicsChannel Thanks for quick reply! I manage to understand most of the code except for one thing, "delay equalizer", can you elaborate on that part? What if i remove the code?
@@nova0302 Nice!! The "delay equalize" is a trick used to make the run time of code be the same for different branches.
In this way, we have less jitter on the overall loop, because different paths of the code will need more/less time to execute.
So probably I added the "delay equalizer" in a fast section of the code, to make the execution time of that branch more even in respect to other branches of code
😍Thank you
It is great!!!
Glad you liked!
@@AllElectronicsChannel Sorry, can't find a way to contact with you, but really like your videoes, and could you help to confirm, if I can post your video on my channel, to spread your great energy?
can anyone give real world examples for coth a corporate level and personal use level of this concept
Real world examples?? Your message arrived at my phone passing 500 levels of clock recovery through all digital media it traveled!! 😝😝😝
baud rate is the same as symbol rate and should be in symbols/sec instead of bits/sec...some information can be misleading, so I tend to take it with a grain of salt...
😉😉
❤
Wow
wow!
The best thing i did today is cmng across your channel, its our channel❤
Hi sir
👍🤗
😇😇
🙏🙏🌹🌹🌹🌹