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- เผยแพร่เมื่อ 16 พ.ค. 2017
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Learn how a clock drives all sequential logic in your FPGA, from Flip-Flops to Block RAMs. The clock tells you how fast you can run your FPGA. This video demonstrates how to properly deal with multiple clock domains inside your design. I present an example showing how to turn a 40 MHz clock into a 10 MHz clock using Clock Enable pulses.
Link to the EDA Playground Verilog code and simulation:
www.edaplayground.com/x/vud
Link to the Crossing Clock Domains page on my website:
www.nandland.com/articles/cro...
Support this channel! Buy a Go Board, the best development board for beginners to FPGA: www.nandland.com/goboard/intr...
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/ nandland - วิทยาศาสตร์และเทคโนโลยี
As a beginner I find myself going to your website and your videos to try and figure out what my teacher was talking about....thanks for explaining in a clear simple manner......you should teach...... :)
"Kchunk" love it
The example code & simulations are very helpful!
Amazing videos! Thank you so much! Go board was the best purchase for me to learn about FPGA
Don't know how to thank you, I was looking for an answer how a distribution of clocks works. You explained it very well and clear.
There's always Patreon! Patreon.com/nandland. It really helps!
11:41 *slaps cat off table* lol
Its an awesome presentation thanks for your video....waiting for more.
Thank you very much!! Loved your video and learnt so much!! Keep up the great stuff!!
thanks a bunch... I watched your initial videos from 2015 and I was you had an updated version. On finding this, I concluded you are the bomb. Now I can deliver better and informed understanding on FPGAs. Yes, grow your beard back.
great video as always!
Haha, I've done excatly that! used an baud clk signal to drive a FIR, opps :(. The videos are great, really clear and detailed, thanks. Nice cat swip, ha.
nice explanation for beginners
Very helpful and clear!
great explanation
I love your website
so much value thank's man
Important point: Since the enable signal is generated from the base 40MHz clock, using enable true in conjunction with the rising edge of the 40MHz clock happens at the 2nd edge since the enable happens - in real time - after the first rising edge of the base clock.
Remember propagation delays as well as setup and hold specs in the “real world”!
Thank you very much!
Thank you sir :)
I love your videos
Thank you!
Sir, your videos are just awesome. I am learning a lot about FPGAs from your video tutorials. I have a query regarding the crossing clock domain. As you said, we have to deal with it gingerly while transferring data faster domain to slower domain and vice-versa. In these cases, can we use a FIFO buffer?
And also, Thanks a lot for this initiative. Keep making such videos.
If only I made a video about just that topic... oh wait! th-cam.com/video/eyNU6mn_-7g/w-d-xo.html
Thank you for your videos man! Could you do one on timing closure?
btw, where is the image at 3:06 from? I think I've seen it in some book.. but I can't quite place it...
I'll add it to the list. I found it via google image search.
Hey great video, i can finally understand more about the inner working of CTS. But i have a question. What does it mean when you say the 10MHz clock cannot be used internally? Does it means i cant create one module of 10MHz ADC clock like you did and channel it throughout the FPGA for other sequential circuit that requires it?If it can be used externally where it is place? As another pin? Anyone can clarify?
Damn TH-cam - I wish to give more than one like.
I'm curious how I would generate a 25.2MHz VGA clk from my 50MHz Ext Osc. The ratio is 63/125, but I can see any sensible way to apply any non-power of two division to a clock. So far I have just been using ALTPLL.
can you please tell me why the test signal increment at the falling edge of clock_EN and not the rising edge ? THANK YOU
Hey is it possible to generate 100MHz clock from FPGA and give it PMOD headers to use it outside.if possible,how?
Would it be more power efficient to use a PLL to divide the main clock versus the example you gave of dividing the clock manually in verilog?
Just to be clear I'm not dividing the clock... I'm using a clock enable. And to answer your question definitely clock enable is more power efficient. PLLs take 10-100s of mW of power. They're more useful for creating clocks that are out of phase with eachother and have no relationship. E.g. 100 MHz and 121 MHz or something like that a PLL is good for.
in the adc code : condition should be r_Clock_count
Ok, I hear the message, and I want to adapt my code to follow your recommendation. So, until now, I did reuse the divided-down clock "clk_div" to drive another process, whose first statement (in VHDL) was "if rising_edge(clk_div) then". What would the beginning of the process now look like when using the clock-enable approach?
If rising_edge(clk) then
If (clk_en) then
Do stuff
Did you say there's a way to go *faster* than the main 25Mhz clock on the Go board? I'm curious because I'd love to construct my own Ethernet interface circuitry eventually.
Not without replacing the main oscillator on the Go Board. There's no PLL on this particular FPGA.
I would expect r_Test to increase on the rising edge of o_ADC_Clock, but instead it is delayed. What’s happening here ?
I'm confused. You said don't use o_ADC_Clock as a clock, because it's an output from a flip-flop, so why is it okay to use r_Clock_En as a clock? Isn't that also the output of a flip-flop?
super
I would not rely on a default assignment in a clocked process with non-blocking assignment. Your code will be subject to race conditions and may have a different behaviour depending on the simulator.
Hm, not sure exactly what code you're referring to... but I've done default assignments in clocked processes for years and never had a problem across Lattice, Altera, and Xilinx FPGAs and synthesis tools.
"The ADC clock is not used internally, because it's the output of a flop-flop" You've tried to explain why, but I still don't get it right I think. Does it has to do with timing? (like the output of a flipflop is that current edge unreliable?
I have a pretty dumb question, and I’m super new to digital design as I come moreso from a software/programming background, so please bear with me lol.
You talked about how you’ve made projects for interfacing with a camera. Why would you want to design something with an FPGA to do stuff like that as opposed to using a microcontroller like arduino?
I guess this question sort of applies to a lot of digital systems work in general. If a lot of this stuff can be implemented in software and/or with microcontrollers, why design use FPGA’s instead?
If you can do it in a microcontroller, you should. FPGAs are more complicated and take more engineering effort to do the same task. However sometimes you can't use a microcontroller, they're just not fast enough. I doubt you could get an Arduino to process data fast enough from a high pixel / frame rate camera.
hello sir, tell me if im wrong but i thought o_ADC_Clock is suppose to be 10 MHz but instead it is 20MHz( it operates 1 cycle every 2 cycles of 40MHz wave).
I believe a clock so high can heat a lot, and burn the circuit.
Can you do machine vision with this board?
Almost certainly no. I don't know what's required for that, but it's probably something a lot more powerful and a lot more expensive.
Great
Is it a latch when r_Clock_Count == 1 or 3?
Interesting. Based on my understanding its not always good to use logic for clock prescsler. It will be not as clean as from PLL. Jitter performance should be much better. And when you run 100MHz 16MHz adc you need few ps jitter in order not to generate tones that are not in your signal
Using a flop output as a clock input is such a schoolboy error. This burns lots of folks when they first start playing with FPGAs. It usually works in the simple "flashing an LED" examples, but, then burns you for anything more complex!
how r_Clock_Count went back to 0 ? Can someone tell me its a mystery to me!
OK..I figured it out...Its actually very interesting. I've never seen anyone using that kind of technic.
Since we use b'00 wide register the max number is 3, when its going to hit 4 its going to overflow and turn everything to b'00
@@viscoreviscore2417 Indeed.
5:20 You are wrong about processors doing one instruction at a time. In fact, modern processors have hundreds to thousands of inflight instructions. And basically the processors are also made out of millions of combinational logic gates and sequential logic elements i.e. flip-flops. So, potentially all those millions of flip-flops in a processor can also toggle in any given cycle. But in either a processor or an fpga, the percentage of all flip-flops that might toggle in any given cycle is less than 50% statistically.
The duty cycle created here is uneven.
Oh, and by popular vote, you need to grow your beard back.
Grow back your beard. We miss it.
I've been watching this video for 5 min thinking that he looks much younger and different in this video and I only realized why, because of your comment :-D