Timing report and RTL schematic interpretation
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- เผยแพร่เมื่อ 16 ก.ค. 2024
- Hi, I'm Stacey, and in this video I show you how to view the schematic for your design, and how to interpret the timing report.
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0:00 TL;DR
0:19 Intro
0:38 Opening the schematic
0:55 Interpreting the schematic
2:42 Generating the timing report
2:57 Interpreting the timing report: slack
4:29 Interpreting the timing report: fanout
5:29 Interpreting the timing report: other values
6:28 Interpreting the timing report: hold
7:39 Summary
8:14 Outro
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Hello! I am not a beginner but I appreciate a good introduction! Your channel is one of very few resources that is useful for beginners. This is a great introduction for beginners. But you made one comment I don't agree with. You state to not look at timing post synthesis. I'm not sure if your intention was to keep it simple for beginners or if you're not aware of how powerful a tool looking at the post synthesis timing estimates are. It really helps as post implementation the nets that fail are very often not problematic nets. Often Vivado can get your net with to many levels of logic to close timing, but then fails on your flop to flop paths because of congestion. Same is true if you forget to take advantage of input/output registers on BRAMs/DSPs. Post synthesis will actually reveal these problematic nets.
Hi James! Thanks for your comment. You're absolutely correct. I was aiming for keeping things simple but watching this back, I definitely feel like I went a bit too far by explicitly saying not to look at the synthesis timing report. I've removed that bit at the end. Thanks for pointing this out!
Hi again James! I'm making a list of professionals who can help vet my videos before they go public, to pick up errors like this. If that's something you'd be interested in, you're welcome to email me at hdlforbeginners@gmail.com and I'd be happy to send you an unlisted link to videos. Thanks! (And anyone else out there who's a professional, you're welcome to give feedback too!)
@@FPGAsforBeginners No problem, glad I could help! I'd be happy to give feedback for future videos.
for me this part and a @factory@ one was very important to understand something i have missed. bravo! thanks
Thanks for these videos. Its nice to see someone cover these topics and with clear simple explanations. Keep up the great work.
Very informative, thank you and please keep going :)
Great video, Stacy.
Very helpful.
Thanks
Excellent explanation! I whish I discovered this earlier!
Perfect explanation.
hello Thank you for making such a good video it was very useful
Thanks for sharing this, please add a negative time slack example and show how to find it and solve it🌱
Thanks for the videos, really helpful, I took two digital design with VHDL courses all the way back in 2010, we covered quite a lot but for some reason not much was done on pratcial timing analysus problems and how to work through them
I had absolutely zero education on timing analysis. And I went to school for electronics engineering! This is the first time I'm seeing a tutorial about it on youtube as well.
Hi Stacey. Really enjoyed your clear presentation - it confirmed a lot of things I'm just running through for the 1st time with Vivado. I too am using the Arty-Z7. Wanted to know if you go deeper into this tpic in another video. One thing I've not found elsewhere is how to increase that interprocess setup (or hold) list? What is making the list only 10 items? And as a more spot on question how can one expand it to a specific end to end point?
In my Zynq design I've got some memory mapped HDL registers that is passing constraints. So far good. I see the timing reports focus on the top 10 worse case timing slack endpoints...again all passing but I want to know about unreported signal timing margins. Have not found an answer skimming constraints guides or Xilinx docs & 3rd party Vivado timing help videos (yours was the best of all the ones I've reviewed). If interested in specifics: I've got a 32bit data bus from the AXIBRAM Lite IP to my HDL and in the HDL I do some memory bus decoding & writing to a final register point that happens to be an integer. The decoding works but I want to flesh out why I needed to pipeline aspects of it to get it to work. I want to measure that propagation time or ANY propagation delay between two end points of my choice. Am striking out looking through docs & tutorial videos so would appreciate any related suggestions. With sincere thanks for your sharing these videos and your talents. Cheers.
hi, nice videos! i use the gowin interface though (would love to see some examples in other fpgas manufacturers platforms )
So much understandeble, thanks a lot!
Hello from Ukraine:)
Thank you for the helpful information. If the worst slack is (-1.524nsec) and the clock period of the whole system is (13.468nsec). Is the design acceptable or not? Thanks, a lot.
hi I have doubt about how to calculate area of a circuit in xilinx software.
Are you planning to do a video in which you resolve some typical timing issues? :)
yup! I will. Thanks!
Make a video on clock domain crossing .
Yes! I will add it to my list. Great suggestion!
The space right before the period at the end of this comment is where the word "please" was suppose to go.
Thank you for the helpful information. If the timing reports a negative blue number of the worst slack, is the design acceptable or not?
The number is called "worst case negative slack". So disregarding the word negative in the name, if the number is blue, it should be positive. If the number is red, it should be negative. I don't think I've ever seen a blue negative number (excluding the "negative" in the name, the actual number being negative). Usually red is negative (bad) and blue is positive (good).
Thank you very much for your answer.
In my Timming summary shows NA......what is the solution......?¿
Register your pin inputs and outputs, and make sure your register has a valid clock.
This n/a means that your signals don't have two registers in the path through the device. The timing measurement is from one register to another. No registers -> no timing info.